Introduction

The Intel® 6700PXH 64-bit PCI Hub is a peripheral chip that performs PCI bridging functions between the PCI Express* interface and the PCI Bus. The Intel® 6700PXH 64-bit PCI Hub contains two PCI bus interfaces that can be independently configured to operate in PCI (33 or 66 MHz) or PCI-X Mode 1 (66, 100, or 133 MHz), for either 32 or 64 bit PCI devices.

The Intel® 6700PXH 64-bit PCI Hub further supports the new PCI Standard Hot-Plug Controller and Subsystem Specification Revision 1.0. Each PCI interface contains an I/OxAPIC with 24 interrupts and a standard hot plug controller.

Intel® 6700PXH 64-bit PCI Hub Features

• PCI Express* Interface

— Compatible with PCI Express Base Specification 1.0a

— Compatible with PCI Express Base Specification 1.0a

— Raw bit-rate on the data pins of 2.5 Gbit/s, resulting in a raw bandwidth per pin of 250 MB/ s

— x8 and x4 modes of operation, support for x4 on 3:0 (with 3 being lane 3) and 4:7 (with 4 being lane 3)

— Support for x8, x4 lane reversal

— Support for x4 lane reversal only on the lower 4 lanes

— Maximum realized bandwidth (in x8 mode) on PCI Express* interface is 2 GB/s in each direction simultaneously, for an aggregate of 4 GB/s

— Full-speed self-test and diagnostic (IBIST) functionality

— Automatic link initialization, configuration and re-training out of reset

— Runtime detection and recovery for loss of link synchronization

• PCI(X) Interface

— PCI Spec rev 2.3 compliant

— PCI-X 1.0b spec compliant

— 64-bit 66MHz, 3.3V

— 6 external REQ/GNT Pairs for internal arbiter (only 3 pairs are available when operating SHPC in parallel mode)

— On-die termination of 8.33K ohms @ 40

— 64 bit addressing, inbound and outbound and support for DAC command

— Full peer-to-peer read and write capability between the two PCI segments in Intel® 6700PXH 64-bit PCI Hub

• RAS Features

— PCI Express* interfaces protected with 32-bit CRC

— Full access to all registers via SMBus

— PCI bus protected with parity

• PCI standard Hot Plug

— PCI Standard Hot-Plug controller Specification Rev 1.0 compliant

— PCI Standard Hot-Plug controller Specification Rev 1.0 compliant

— Two controllers - one for each PCI bus segment

— Support for 6 slots maximum

— Parallel mode operation for 1 and 2 slot systems and slot interface logic not needed.

— Serial mode operation for other systems with hot-plug slots from 3 to 6. Slot interface logic needed to serialize and de-serialize information from Intel® 6700PXH 64-bit PCI Hub

— 1-slot-no-glue parallel mode operation when the number of slots controlled is one and there are no other devices on the PCI bus. No on-board Q-Switches are needed for bus isolation in this mode

• I/OXAPIC

— One I/OxAPIC controller per PCI bus segment

— 24 interrupts per controller

— 16 physical PCI interrupt pins per PCI bus in the server mode

— PCI virtual wire interrupt support via writing to Pin Assertion Register in the I/OxAPIC

• SMBus Interface

— Electrically compliant with System Management Bus 2.0 Specification with PEC support

— Slave mode operation only

— Full read/write access to all configuration and memory spaces in Intel® 6700PXH 64-bit PCI Hub

• Power Management

— Support for PCI Express* Active State Power Management (ASPM) L0s link state

— Support for PCI PM 1.1 compatible D0, D3hot and D3cold device power states

— Support for PME# event propagation on behalf of PCI devices