1 Summary of Features

The TC37x product family has the following features:

• High Performance Microcontroller with three CPU cores

• Three 32-bit super-scalar TriCore CPUs (TC1.6.2P), each having the following features:

– Superior real-time performance

– Strong bit handling

– Fully integrated DSP capabilities

– Multiply-accumulate unit able to sustain 2 MAC operations per cycle

– Fully pipelined Floating point unit (FPU)

– up to 300 MHz operation at full temperature range

– up to 240/96 Kbyte Data Scratch-Pad RAM (DSPR)

– up to 64 Kbyte Instruction Scratch-Pad RAM (PSPR)

– 32 Kbyte Instruction Cache (ICACHE)

– 16 Kbyte Data Cache (DCACHE)

• Lockstepped shadow cores for up to two TC1.6.2P

• Multiple on-chip memories

– All embedded NVM and SRAM are ECC protected

– up to 6 Mbyte Program Flash Memory (PFLASH)

– up to 384 Kbyte Data Flash Memory (DFLASH) usable for EEPROM emulation

– BootROM (BROM)

• 128-Channel DMA Controller with safe data transfer

• Sophisticated interrupt system (ECC protected)

• High performance on-chip bus structure

– 64-bit Cross Bar Interconnect (SRI) giving fast parallel access between bus masters, CPUs and memories

– 32-bit System Peripheral Bus (SPB) for on-chip peripheral and functional units

– SRI to SPB bus bridges (SFI Bridge)

• Optional Hardware Security Module (HSM) on some variants

• Safety Management Unit (SMU) handling safety monitor alarms

• Memory Test Unit with ECC, Memory Initialization and MBIST functions (MTU)

• Hardware I/O Monitor (IOM) for checking of digital I/O

• Versatile On-chip Peripheral Units

– 12 Asynchronous/Synchronous Serial Channels (ASCLIN) with hardware LIN support (V1.3, V2.0, V2.1

and J2602) up to 50 MBaud

– 5 Queued SPI Interface Channels (QSPI) with master and slave capability up to 50 Mbit/s

– 1 High Speed Serial Link (HSSL) for serial inter-processor communication up to 320 Mbit/s

– 2 serial Micro Second Bus interfaces (MSC) for serial port expansion to external power devices

– 2 MCMCAN Modules with 4 CAN nodes for high efficiency data handling via FIFO buffering

– 15 Single Edge Nibble Transmission (SENT) channels for connection to sensors

– 1 FlexRayTM module with 2 channels (E-Ray) supporting V2.1

– One Generic Timer Module (GTM) providing a powerful set of digital signal filtering and timer functionality to realize autonomous and complex Input/Output management

– One Capture / Compare 6 module (Two kernels CCU60 and CCU61)

– One General Purpose 12 Timer Unit (GPT120)

– 2 channel Peripheral Sensor Interface conforming to V1.3 (PSI5)

– 1 Peripheral Sensor Interface with Serial PHY (PSI5-S)

– 1 Inter-Integrated Circuit Bus Interface (I2C) conforming to V2.1

– 1 IEEE802.3 Ethernet MAC with RMII and MII interfaces (ETH)

• Versatile Successive Approximation ADC (VADC)

– Cluster of 12 independent ADC kernels

– Input voltage range from 0 V to 5.5V (ADC supply)

• Delta-Sigma ADC (DSADC)

– 6 channels

• Digital programmable I/O ports

• On-chip debug support for OCDS Level 1 (CPUs, DMA, On Chip Buses)

• multi-core debugging, real time tracing, and calibration

• four/five wire JTAG (IEEE 1149.1) or DAP (Device Access Port) interface

• Power Management System and on-chip regulators

• Clock Generation Unit with System PLL and Peripheral PLL

• Embedded Voltage Regulator