Introduction

The C164CI derivatives of the Infineon C166 Family of full featured single-chip CMOS microcontrollers are especially suited for cost sensitive applications. They combine high CPU performance (up to 12.5 million instructions per second) with high peripheral functionality and enhanced IO-capabilities. They also provide clock generation via PLL and various on-chip memory modules such as program ROM or OTP, internal RAM, and extension RAM.

16-Bit Single-Chip Microcontroller C164CI C166 Family

C164CI/SI, C164CL/SL

• High Performance 16-bit CPU with 4-Stage Pipeline

– 80 ns Instruction Cycle Time at 25 MHz CPU Clock

– 400 ns Multiplication (16 × 16 bit), 800 ns Division (32 / 16 bit)

– Enhanced Boolean Bit Manipulation Facilities

– Additional Instructions to Support HLL and Operating Systems

– Register-Based Design with Multiple Variable Register Banks

– Single-Cycle Context Switching Support

– 16 MBytes Total Linear Address Space for Code and Data

– 1024 Bytes On-Chip Special Function Register Area

• 16-Priority-Level Interrupt System with 32 Sources, Sample-Rate down to 40 ns

• 8-Channel Interrupt-Driven Single-Cycle Data Transfer Facilities via Peripheral Event Controller (PEC)

• Clock Generation via on-chip PLL (factors 1:1.5/2/2.5/3/4/5), via prescaler or via direct clock input

• On-Chip Memory Modules

– 2 KBytes On-Chip Internal RAM (IRAM)

– 2 KBytes On-Chip Extension RAM (XRAM)

– up to 64 KBytes On-Chip Program Mask ROM or OTP Memory

• On-Chip Peripheral Modules

– 8-Channel 10-bit A/D Converter with Programmable Conversion Time down to 7.8 µs

– 8-Channel General Purpose Capture/Compare Unit (CAPCOM2)

– Capture/Compare Unit for flexible PWM Signal Generation (CAPCOM6) (3/6 Capture/Compare Channels and 1 Compare Channel)

– Multi-Functional General Purpose Timer Unit with 3 Timers

– Two Serial Channels (Synchronous/Asynchronous and High-Speed-Synchronous)

– On-Chip CAN Interface (Rev. 2.0B active) with 15 Message Objects (Full CAN/Basic CAN)

– On-Chip Real Time Clock

• Up to 4 MBytes External Address Space for Code and Data

– Programmable External Bus Characteristics for Different Address Ranges

– Multiplexed or Demultiplexed External Address/Data Buses with 8-Bit or 16-Bit Data Bus Width

– Four Optional Programmable Chip-Select Signals

• Idle, Sleep, and Power Down Modes with Flexible Power Management

• Programmable Watchdog Timer and Oscillator Watchdog

• Up to 59 General Purpose I/O Lines, partly with Selectable Input Thresholds and Hysteresis

• Supported by a Large Range of Development Tools like C-Compilers, Macro-Assembler Packages, Emulators, Evaluation Boards, HLL-Debuggers, Simulators, Logic Analyzer Disassemblers, Programming Boards

• On-Chip Bootstrap Loader

• 80-Pin MQFP Package, 0.65 mm pitch