Device overview

• Architecture

- Infineon 45-nm MIRRORBIT™ technology that stores two data bits in each memory array cell

- Sector architecture

• Uniform 128 KB (2bpc) sectors

• Uniform 64 KB (1bpc) sectors

• Configurable sector architecture options for 128 KB (2bpc) and 64 KB (1bpc) sectors

- Page programming buffer of 256 or 512 bytes

- OTP secure silicon array of 1024 bytes (32  32 bytes)

• Interface

- SPI

• Supports 1S-1S-1S protocols

• Runs up to 13 MBps (104 MHz clock speed)

- Quad

• Supports 1S-1S-4S, 1S-4S-4S protocols

• Runs up to 52 MBps (104 MHz clock speed)

• Highlights

- Built-in error correcting code (ECC) corrects single-bit error and detects 2-bit error on memory array data

- Ready Busy (RD/BY# = LOW) indicates that an internal event is ongoing

- Hardware reset through CS# signaling method (JEDEC) or individual RESET# pin

• Identification

- Serial flash discoverable parameters (SFDP) describing device functions and features

- Device identification, manufacturer identification, and unique identification

• Data integrity (100 ECC protection)

- Program-erase cycles

• 1bpc sectors minimum 100K cycles

• 2bpc sectors minimum 5K cycles

- Data retention

• 1bpc sector end of life minimum 0.28 year retention

• 2bpc sector end of life minimum 25 years retention

• Supply voltage

- 1.7-V to 2.0-V

• Grade/temperature range

- Commercial (0°C to +70°C)

- Industrial (–40°C to +85°C)

• Packages

- Known good wafer (KGW) (Contact Sales)

- 24-ball BGA 6  8 mm

- Wafer level chip scale package (WLCSP)