Features

• CPU subsystem

- One or two[1] 250-MHz 32-bit Arm® Cortex®-M7 CPUs, each with

• Single-cycle multiply

• Single/double-precision floating point unit (FPU)

• 16-KB data cache, 16-KB instruction cache

• Memory protection unit (MPU)

• 16-KB instruction and 16-KB data tightly-coupled memories (TCM)

- 100-MHz 32-bit Arm® Cortex® M0+ CPU with

• Single-cycle multiply

• MPU

- Inter-processor communication in hardware

- Three DMA controllers

• Peripheral DMA controller #0 (P-DMA0) with 100 channels

• Peripheral DMA controller #1 (P-DMA1) with 58 channels

• Memory DMA controller (M-DMA0) with 8 channels

• Integrated memories

- 4160 KB of code-flash with an additional 256 KB of work-flash

• Read-While-Write (RWW) allows updating the code-flash/work-flash while executing from it

• Single- and dual-bank modes (specifically for Firmware update Over The Air [FOTA])

• Flash programming through SWD/JTAG interface

- 768 KB of SRAM with selectable retention granularity

• Cryptography engine

- Supports enhanced Secure Hardware Extension (eSHE) and Hardware Security Module (HSM)

- Secure boot and authentication

• Using digital signature verification

• Using fast secure boot

- AES: 128-bit blocks, 128-/192-/256-bit keys

- 3DES: 64-bit blocks, 64-bit key

- Vector unit supporting asymmetric key cryptography such as Rivest-Shamir-Adleman (RSA) and Elliptic Curve

(ECC)

- SHA-1/2/3: SHA-512, SHA-256, SHA-160 with variable length input data

- CRC: supports CCITT CRC16 and IEEE-802.3 CRC32

- True random number generator (TRNG) and pseudo random number generator (PRNG)

- Galois/Counter Mode (GCM)