Features

32-bit MCU Subsystem

■ 48-MHz ARM Cortex-M0+ CPU

■ Up to 32 KB of flash with Read Accelerator

■ Up to 4 KB of SRAM

Programmable Analog

■ Single-slope 10-bit ADC function provided by Capacitance

sensing block

■ Two current DACs (IDACs) for general-purpose or capacitive

sensing applications on any pin

■ Two low-power comparators that operate in Deep Sleep

low-power mode

Programmable Digital

Programmable logic blocks allowing Boolean operations to be

performed on port inputs and outputs

Low-Power 1.71-V to 5.5-V Operation

■ Deep Sleep mode with operational analog and 2.5 A digital

system current

Capacitive Sensing

■ Cypress CapSense Sigma-Delta (CSD) provides best-in-class

signal-to-noise ratio (SNR) (>5:1) and water tolerance

■ Cypress-supplied software component makes capacitive

sensing design easy

■ Automatic hardware tuning (SmartSense™)

Serial Communication

■ Two independent run-time reconfigurable Serial

Communication Blocks (SCBs) with re-configurable I2C, SPI,

or UART functionality

LCD Drive Capability

■ LCD segment drive capability on GPIOs

Timing and Pulse-Width Modulation

■ Five 16-bit timer/counter/pulse-width modulator (TCPWM)

blocks

■ Center-aligned, Edge, and Pseudo-random modes

■ Comparator-based triggering of Kill signals for motor drive and

other high-reliability digital logic applications

Up to 36 Programmable GPIO Pins

■ 48-pin TQFP, 40-pin QFN, 32-pin QFN, 24-pin QFN, and

25-ball WLCSP packages

■ Any GPIO pin can be CapSense, analog, or digital

■ Drive modes, strengths, and slew rates are programmable

PSoC Creator Design Environment

■ Integrated Development Environment (IDE) provides

schematic design entry and build (with analog and digital

automatic routing)

■ Applications Programming Interface (API) component for all

fixed-function and programmable peripherals

Industry-Standard Tool Compatibility

■ After schematic entry, development can be done with

ARM-based industry-standard development tools