Features

• VDSS = 1200 V at Tvj = -55...175°C

• IDDC = 34 A at TC = 25°C

• RDS(on) = 80 mΩ at VGS = 20 V, Tvj = 25°C

• New performance-optimized chip technology (Gen1p) with improved RDSon* A

• Best in class switching energy for lower switching losses and reduced cooling efforts

• Lowest device capacitances for higher switching speeds and higher power density

• A combination of low Crss/Ciss ratio and high VGS(th) to avoid parasitic turn-on and enable unipolar

gate driving

• Reduced total gate charge QG for lower driving power and losses

• Increased recommended turn-on voltage (VGS(on) = 20 V) for lower RDS(on)

• .XT die attach technology for best in class thermal performance

• Low package stray inductance for faster and cleaner switching

• Drive (Kelvin) Source pin for better gate control and reduced switching losses

• Creepage distance > 4.75 mm fitting Vrms(max) > 950 V based on IEC60664 for material group I,

pollution degree 2

• SMT package for automated assembly and reduced system costs

• Low Rth Top-Side Cooled package for best thermal performance and power density