DESCRIPTION:

The IDT72T51546/72T51556 multi-queue flow-control devices is a single chip within which anywhere between 1 and 32 discrete FIFO queues can be setup. All queues within the device have a common data input bus, (write port) and a common data output bus, (read port). Data written into the write port is directed to a respective queue via an internal de-multiplex operation, addressed by the user. Data read from the read port is accessed from a respective queue via an internal multiplex operation, addressed by the user. Data writes and reads can be performed at high speeds up to 200MHz, with access times of 3.6ns. Data write and read operations are totally independent of each other, a queue maybe selected on the write port and a different queue on the read port or both ports may select the same queue simultaneously.

FEATURES:

• Choose from among the following memory density options:

IDT72T51546  Total Available Memory = 1,179,648 bits

IDT72T51556  Total Available Memory = 2,359,296 bits

• Configurable from 1 to 32 Queues

• Queues may be configured at master reset from the pool of Total Available Memory in blocks of 256 x 36

• Independent Read and Write access per queue

• User programmable via serial port

• User selectable I/O: 2.5V LVTTL, 1.5V HSTL, 1.8V eHSTL

• Default multi-queue device configurations

– IDT72T51546 : 1,024 x 36 x 32Q

– IDT72T51556 : 2,048 x 36 x 32Q

• 100 Bus Utilization, Read and Write on every clock cycle

• 200 MHz High speed operation (5ns cycle time)

• 3.6ns access time

• Echo Read Enable & Echo Read Clock Outputs

• Individual, Active queue flags (OV, FF, PAE, PAF, PR)

• 8 bit parallel flag status on both read and write ports

• Shows PAE and PAF status of 8 Queues

• Direct or polled operation of flag status bus

• Global Bus Matching - (All Queues have same Input Bus Width and Output Bus Width)

• User Selectable Bus Matching Options:

– x36in to x36out

– x18in to x36out

– x9in to x36out

– x36in to x18out

– x36in to x9out

• FWFT mode of operation on read port

• Packet mode operation

• Partial Reset, clears data in single Queue

• Expansion of up to 8 multi-queue devices in parallel is available

• Power Down Input provides additional power savings in HSTL and eHSTL modes.

• JTAG Functionality (Boundary Scan)

• Available in a 256-pin PBGA, 1mm pitch, 17mm x 17mm

• HIGH Performance submicron CMOS technology

• Industrial temperature range (-40°C to +85°C) is available