Description

The IDT71V35761/781 are high-speed SRAMs organized as 128K x 36/256K x 18. The IDT71V35761/781 SRAMs contain write, data, address and control registers. Internal logic allows the SRAM to generate a self-timed write based upon a decision which can be left until the end of the write cycle.

Features

◆128K x 36, 256K x 18 memory configurations

◆Supports high system speed:

Commercial:

– 200MHz 3.1ns clock access time

Commercial and Industrial:

– 183MHz 3.3ns clock access time

– 166MHz 3.5ns clock access time

◆LBOinput selects interleaved or linear burst mode

◆Self-timed write cycle with global write control (GW), byte write enable (BWE), and byte writes (BWx)

◆3.3V core power supply

◆Power down controlled by ZZ input

◆3.3V I/O

◆Optional - Boundary Scan JTAG Interface (IEEE 1149.1 compliant)

◆Packaged in a JEDEC Standard 100-pin plastic thin quad flatpack (TQFP), 119 ball grid array (BGA) and 165 fine pitch ball grid array