In-System Programmable High Density PLD

Description The ispLSI 2032 and 2032A are High Density Programmable Logic Devices. The devices contain 32 Registers, 32 Universal I/O pins, two Dedicated Input Pins, three Dedicated Clock Input Pins, one dedicated Global OE input pin and a Global Routing Pool (GRP). The GRP provides complete in

In-System Programmable High Density PLD

In-System Programmable High Density PLD

Description\nThe ispLSI 2032 and 2032A are High Density Programmable Logic Devices. The devices contain 32 Registers, 32 Universal I/O pins, two Dedicated Input Pins, three Dedicated Clock Input Pins, one dedicated Global OE input pin and a Global Routing Pool (GRP). The GRP provides complete interc • ENHANCEMENTS\n   — ispLSI 2032A is Fully Form and Function Compat to the ispLSI 2032, with Identical Timing Specifcations and Packaging\n   — ispLSI 2032A is Built on an Advanced 0.35 Micron E2CMOS® Technology\n• HIGH DENSITY PROGRAMMABLE LOGIC\n   — 1000 PLD Gates\n   — 32 I/O Pins, Two Dedicated;

In-System Programmable High Density PLD

Description The ispLSI 2032 and 2032A are High Density Programmable Logic Devices. The devices contain 32 Registers, 32 Universal I/O pins, two Dedicated Input Pins, three Dedicated Clock Input Pins, one dedicated Global OE input pin and a Global Routing Pool (GRP). The GRP provides complete in