VR11.1 Compatible Synchronous Rectified Buck MOSFET Drivers

VR11.1, 4-Phase PWM Controller with Light Load Efficiency Enhancement and Load Current Monitoring Features The ISL6334B, ISL6334C control microprocessor core voltage regulation by driving up to 4 interleaved synchronous-rectified buck channels in parallel. This multiphase architecture resul

VR11.1 Compatible Synchronous Rectified Buck MOSFET Drivers

The ISL6620, ISL6620A is a high frequency MOSFET driver designed to drive upper and lower power N-Channel MOSFETs in a synchronous rectified buck converter topology. The advanced PWM protocol of ISL6620, ISL6620A is specifically designed to work with Intersil VR11.1 controllers and combined w

封装/外壳：10-VFDFN 裸露焊盘 包装：卷带（TR） 描述：IC GATE DRVR HALF-BRIDGE 10DFN 集成电路（IC） 栅极驱动器

VR11.1 Compatible Synchronous Rectified Buck MOSFET Drivers

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封装/外壳：10-VFDFN 裸露焊盘 包装：卷带（TR） 描述：IC GATE DRVR HALF-BRIDGE 10DFN 集成电路（IC） 栅极驱动器

65 MSPS Digital Receive Signal Processor

GENERAL DESCRIPTION The AD6620 is a digital receiver with four cascaded signal-processing elements: a frequency translator, two fixed-coefficient decimating filters, and a programmable coefficient decimating filter. All inputs are 3.3 V LVCMOS compatible. All outputs are LVCMOS and 5 V TTL compat

65 MSPS Digital Receive Signal Processor

GENERAL DESCRIPTION The AD6620 is a digital receiver with four cascaded signal-processing elements: a frequency translator, two fixed-coefficient decimating filters, and a programmable coefficient decimating filter. All inputs are 3.3 V LVCMOS compatible. All outputs are LVCMOS and 5 V TTL compat

67 MSPS Digital Receive Signal Processor

GENERAL DESCRIPTION The AD6620 is a digital receiver with four cascaded signal-processing elements: a frequency translator, two fixed-coefficient decimating filters, and a programmable coefficient decimating filter. All inputs are 3.3 V LVCMOS compatible. All outputs are LVCMOS and 5 V TTL compat

67 MSPS Digital Receive Signal Processor

GENERAL DESCRIPTION The AD6620 is a digital receiver with four cascaded signal-processing elements: a frequency translator, two fixed-coefficient decimating filters, and a programmable coefficient decimating filter. All inputs are 3.3 V LVCMOS compatible. All outputs are LVCMOS and 5 V TTL compat

67 MSPS Digital Receive Signal Processor

文件：399.31 Kbytes Page：44 Pages