位置:首页 > IC中文资料 > IS64VPS12836EC
| 型号 | 功能描述 | 生产厂家 企业 | LOGO | 操作 |
|---|---|---|---|---|
IS64VPS12836EC | Synchronous SRAM | ISSI 矽成半导体 | ||
128K x36/32 and 256K x18 4Mb, ECC, SYNCHRONOUS PIPELINED, SINGLE CYCLE DESELECT SRAM FEATURES Internal self-timed write cycle Individual Byte Write Control and Global Write Clock controlled, registered address, data and control Burst sequence control using MODE input Three chip enable option for simple depth expansion and address pipelining Common data inputs an | ISSI 矽成半导体 | |||
128K x36/32 and 256K x18 4Mb, ECC, SYNCHRONOUS PIPELINED, SINGLE CYCLE DESELECT SRAM FEATURES Internal self-timed write cycle Individual Byte Write Control and Global Write Clock controlled, registered address, data and control Burst sequence control using MODE input Three chip enable option for simple depth expansion and address pipelining Common data inputs an | ISSI 矽成半导体 | |||
128K x36/32 and 256K x18 4Mb, ECC, SYNCHRONOUS PIPELINED, SINGLE CYCLE DESELECT SRAM FEATURES Internal self-timed write cycle Individual Byte Write Control and Global Write Clock controlled, registered address, data and control Burst sequence control using MODE input Three chip enable option for simple depth expansion and address pipelining Common data inputs an | ISSI 矽成半导体 | |||
128K x36/32 and 256K x18 4Mb, ECC, SYNCHRONOUS PIPELINED, SINGLE CYCLE DESELECT SRAM FEATURES Internal self-timed write cycle Individual Byte Write Control and Global Write Clock controlled, registered address, data and control Burst sequence control using MODE input Three chip enable option for simple depth expansion and address pipelining Common data inputs an | ISSI 矽成半导体 | |||
128K x36/32 and 256K x18 4Mb, ECC, SYNCHRONOUS PIPELINED, SINGLE CYCLE DESELECT SRAM FEATURES Internal self-timed write cycle Individual Byte Write Control and Global Write Clock controlled, registered address, data and control Burst sequence control using MODE input Three chip enable option for simple depth expansion and address pipelining Common data inputs an | ISSI 矽成半导体 | |||
128K x36/32 and 256K x18 4Mb, ECC, SYNCHRONOUS PIPELINED, SINGLE CYCLE DESELECT SRAM FEATURES Internal self-timed write cycle Individual Byte Write Control and Global Write Clock controlled, registered address, data and control Burst sequence control using MODE input Three chip enable option for simple depth expansion and address pipelining Common data inputs an | ISSI 矽成半导体 | |||
128K x36/32 and 256K x18 4Mb, ECC, SYNCHRONOUS PIPELINED, SINGLE CYCLE DESELECT SRAM FEATURES Internal self-timed write cycle Individual Byte Write Control and Global Write Clock controlled, registered address, data and control Burst sequence control using MODE input Three chip enable option for simple depth expansion and address pipelining Common data inputs an | ISSI 矽成半导体 | |||
128K x36/32 and 256K x18 4Mb, ECC, SYNCHRONOUS PIPELINED, SINGLE CYCLE DESELECT SRAM FEATURES Internal self-timed write cycle Individual Byte Write Control and Global Write Clock controlled, registered address, data and control Burst sequence control using MODE input Three chip enable option for simple depth expansion and address pipelining Common data inputs an | ISSI 矽成半导体 | |||
128K x36/32 and 256K x18 4Mb, ECC, SYNCHRONOUS PIPELINED, SINGLE CYCLE DESELECT SRAM FEATURES Internal self-timed write cycle Individual Byte Write Control and Global Write Clock controlled, registered address, data and control Burst sequence control using MODE input Three chip enable option for simple depth expansion and address pipelining Common data inputs an | ISSI 矽成半导体 | |||
128K x36/32 and 256K x18 4Mb, ECC, SYNCHRONOUS PIPELINED, SINGLE CYCLE DESELECT SRAM FEATURES Internal self-timed write cycle Individual Byte Write Control and Global Write Clock controlled, registered address, data and control Burst sequence control using MODE input Three chip enable option for simple depth expansion and address pipelining Common data inputs an | ISSI 矽成半导体 | |||
128K x36/32 and 256K x18 4Mb, ECC, SYNCHRONOUS PIPELINED, SINGLE CYCLE DESELECT SRAM FEATURES Internal self-timed write cycle Individual Byte Write Control and Global Write Clock controlled, registered address, data and control Burst sequence control using MODE input Three chip enable option for simple depth expansion and address pipelining Common data inputs an | ISSI 矽成半导体 | |||
128K x36/32 and 256K x18 4Mb, ECC, SYNCHRONOUS PIPELINED, SINGLE CYCLE DESELECT SRAM FEATURES Internal self-timed write cycle Individual Byte Write Control and Global Write Clock controlled, registered address, data and control Burst sequence control using MODE input Three chip enable option for simple depth expansion and address pipelining Common data inputs an | ISSI 矽成半导体 | |||
128K x36/32 and 256K x18 4Mb, ECC, SYNCHRONOUS PIPELINED, SINGLE CYCLE DESELECT SRAM 文件:2.32368 Mbytes Page:36 Pages | ISSI 矽成半导体 | |||
128K x36/32 and 256K x18 4Mb, ECC, SYNCHRONOUS PIPELINED, SINGLE CYCLE DESELECT SRAM 文件:2.32368 Mbytes Page:36 Pages | ISSI 矽成半导体 | |||
128K x36/32 and 256K x18 4Mb, ECC, SYNCHRONOUS PIPELINED, SINGLE CYCLE DESELECT SRAM 文件:2.32368 Mbytes Page:36 Pages | ISSI 矽成半导体 | |||
128K x36/32 and 256K x18 4Mb, ECC, SYNCHRONOUS PIPELINED, SINGLE CYCLE DESELECT SRAM 文件:2.32368 Mbytes Page:36 Pages | ISSI 矽成半导体 | |||
128K x36/32 and 256K x18 4Mb, ECC, SYNCHRONOUS PIPELINED, SINGLE CYCLE DESELECT SRAM 文件:2.32368 Mbytes Page:36 Pages | ISSI 矽成半导体 | |||
128K x36/32 and 256K x18 4Mb, ECC, SYNCHRONOUS PIPELINED, SINGLE CYCLE DESELECT SRAM 文件:2.32368 Mbytes Page:36 Pages | ISSI 矽成半导体 | |||
128K x36/32 and 256K x18 4Mb, ECC, SYNCHRONOUS PIPELINED, SINGLE CYCLE DESELECT SRAM 文件:2.32368 Mbytes Page:36 Pages | ISSI 矽成半导体 | |||
128K x36/32 and 256K x18 4Mb, ECC, SYNCHRONOUS PIPELINED, SINGLE CYCLE DESELECT SRAM 文件:2.32368 Mbytes Page:36 Pages | ISSI 矽成半导体 | |||
128K x36/32 and 256K x18 4Mb, ECC, SYNCHRONOUS PIPELINED, SINGLE CYCLE DESELECT SRAM 文件:2.32368 Mbytes Page:36 Pages | ISSI 矽成半导体 | |||
128K x36/32 and 256K x18 4Mb, ECC, SYNCHRONOUS PIPELINED, SINGLE CYCLE DESELECT SRAM 文件:2.32368 Mbytes Page:36 Pages | ISSI 矽成半导体 | |||
128K x36/32 and 256K x18 4Mb, ECC, SYNCHRONOUS PIPELINED, SINGLE CYCLE DESELECT SRAM 文件:2.32368 Mbytes Page:36 Pages | ISSI 矽成半导体 | |||
128K x36/32 and 256K x18 4Mb, ECC, SYNCHRONOUS PIPELINED, SINGLE CYCLE DESELECT SRAM 文件:2.32368 Mbytes Page:36 Pages | ISSI 矽成半导体 | |||
128K x 32, 128K x 36, 256K x 18 4 Mb SYNCHRONOUS PIPELINED, SINGLE CYCLE DESELECT STATIC RAM DESCRIPTION The ISSIIS61(64)LPS12832A, IS61(64)LPS/VPS12836A and IS61(64)LPS/VPS25618A are high-speed, low-power synchronous static RAMs designed to provide burstable, high-performancememory for communication and networking applications. The IS61(64)LPS12832A is organized as 131,072 words by 32 b | ISSI 矽成半导体 |
| IC供应商 | 芯片型号 | 品牌 | 批号 | 封装 | 库存 | 备注 | 价格 |
|---|---|---|---|---|---|---|---|
ISSI(美国芯成) |
24+ |
TSOP4812.0mm |
7350 |
现货供应,当天可交货!免费送样,原厂技术支持!!! |
|||
ISSI/芯成 |
2450+ |
TSOP48 |
9850 |
只做原厂原装正品现货或订货假一赔十! |
|||
ISSI(美国芯成) |
2021+ |
TSOPI-48 |
499 |
||||
ISSI |
24+ |
SMD |
15600 |
静态随机存取存储器16M(1Mx16)10nsAsync静态随机存取 |
|||
ISSI |
原厂封装 |
9800 |
原装进口公司现货假一赔百 |
||||
ISSI |
23+ |
BGA |
4500 |
ISSI存储芯片在售 |
|||
ISSI, |
25+ |
25000 |
原厂原包 深圳现货 主打品牌 假一赔百 可开票! |
||||
ISSI |
25+ |
PBGA(165) |
3850 |
百分百原装正品 真实公司现货库存 本公司只做原装 可 |
|||
ISSI |
24+ |
TSOP48 |
9000 |
只做原装正品 有挂有货 假一赔十 |
|||
ISSI Integrated Silicon Soluti |
22+ |
48TSOP I |
9000 |
原厂渠道,现货配单 |
IS64VPS12836EC芯片相关品牌
IS64VPS12836EC规格书下载地址
IS64VPS12836EC参数引脚图相关
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- IS64VPS12836A
- IS64VPS12832EC-250TQLA3
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DdatasheetPDF页码索引
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