IS64价格
参考价格：￥52.3908
型号：IS64C25616AL-12CTLA3 品牌：ISSI 备注：这里有IS64多少钱，2026年最近7天走势，今日出价，今日竞价，IS64批发/采购报价，IS64行情走势销售排行榜，IS64报价。| 型号 | 功能描述 | 生产厂家 企业 | LOGO | 操作 |
|---|---|---|---|---|
128K x 8 HIGH-SPEED CMOS STATIC RAM FEATURES • High-speed access time: 12, 15 ns • Low active power: 160 mW (typical) • Low standby power: 1000 μW (typical) CMOS standby • Output Enable (OE) and two Chip Enable (CE1 and CE2) inputs for ease in applications • Fully static operation: no clock or refresh required • TTL compati | ISSI 矽成半导体 |   | ||
128K x 8 HIGH-SPEED CMOS STATIC RAM FEATURES • High-speed access time: 12, 15 ns • Low active power: 160 mW (typical) • Low standby power: 1000 μW (typical) CMOS standby • Output Enable (OE) and two Chip Enable (CE1 and CE2) inputs for ease in applications • Fully static operation: no clock or refresh required • TTL compati | ISSI 矽成半导体 | | ||
256K x 16 HIGH-SPEED CMOS STATIC RAM FEATURES HIGH SPEED: (IS61/64C25616AL) • High-speed access time: 10ns, 12 ns • Low Active Power: 150 mW (typical) • Low Standby Power: 10 mW (typical) CMOS standby LOW POWER: (IS61/64C25616AS) • High-speed access time: 25 ns • Low Active Power: 75 mW (typical) • Low Standby Power: 1 mW (t | ISSI 矽成半导体 | | ||
256K x 16 HIGH-SPEED CMOS STATIC RAM FEATURES HIGH SPEED: (IS61/64C25616AL) • High-speed access time: 10ns, 12 ns • Low Active Power: 150 mW (typical) • Low Standby Power: 10 mW (typical) CMOS standby LOW POWER: (IS61/64C25616AS) • High-speed access time: 25 ns • Low Active Power: 75 mW (typical) • Low Standby Power: 1 mW (t | ISSI 矽成半导体 | | ||
256K x 16 HIGH-SPEED CMOS STATIC RAM FEATURES HIGH SPEED: (IS61/64C25616AL) • High-speed access time: 10ns, 12 ns • Low Active Power: 150 mW (typical) • Low Standby Power: 10 mW (typical) CMOS standby LOW POWER: (IS61/64C25616AS) • High-speed access time: 25 ns • Low Active Power: 75 mW (typical) • Low Standby Power: 1 mW (t | ISSI 矽成半导体 | | ||
256K x 16 HIGH-SPEED CMOS STATIC RAM FEATURES HIGH SPEED: (IS61/64C25616AL) • High-speed access time: 10ns, 12 ns • Low Active Power: 150 mW (typical) • Low Standby Power: 10 mW (typical) CMOS standby LOW POWER: (IS61/64C25616AS) • High-speed access time: 25 ns • Low Active Power: 75 mW (typical) • Low Standby Power: 1 mW (t | ISSI 矽成半导体 | | ||
512K x 8 HIGH-SPEED CMOS STATIC RAM FEATURES HIGH SPEED: (IS61/64C5128AL) • High-speed access time: 10ns, 12 ns • Low Active Power: 150 mW (typical) • Low Standby Power: 10 mW (typical) CMOS standby LOW POWER: (IS61/64C5128AS) • High-speed access time: 25ns • Low Active Power: 75 mW (typical) • Low Standby Power: 1 mW (typi | ISSI 矽成半导体 | | ||
512K x 8 HIGH-SPEED CMOS STATIC RAM FEATURES HIGH SPEED: (IS61/64C5128AL) • High-speed access time: 10ns, 12 ns • Low Active Power: 150 mW (typical) • Low Standby Power: 10 mW (typical) CMOS standby LOW POWER: (IS61/64C5128AS) • High-speed access time: 25ns • Low Active Power: 75 mW (typical) • Low Standby Power: 1 mW (typi | ISSI 矽成半导体 | | ||
512K x 8 HIGH-SPEED CMOS STATIC RAM FEATURES HIGH SPEED: (IS61/64C5128AL) • High-speed access time: 10ns, 12 ns • Low Active Power: 150 mW (typical) • Low Standby Power: 10 mW (typical) CMOS standby LOW POWER: (IS61/64C5128AS) • High-speed access time: 25ns • Low Active Power: 75 mW (typical) • Low Standby Power: 1 mW (typi | ISSI 矽成半导体 | | ||
64K x 16 HIGH-SPEED CMOS STATIC RAM FEATURES IS61C6416AL and IS64C6416AL • High-speed access time: 12 ns, 15ns • Low Active Power: 175 mW (typical) • Low Standby Power: 1 mW (typical) CMOS standby IS62C6416AL and IS65C6416AL • High-speed access time: 35 ns, 45ns • Low Active Power: 50 mW (typical) • Low Standby Power: 100 μ | ISSI 矽成半导体 | | ||
Asynchronous SRAM ·Broad Solution:- x8, x16, and x32 configurations available- 5V/3.3V/1.8V VDD Power Supply- Commercial, Industrial, and Automotive Temperature (-40 °C to 125 °C) support- BGA, SOJ, SOP, sTSOP, TSOP packages available\n·ECC feature available for High Speed Asynchronous SRAMs\n·Long-term support | ISSI 矽成半导体 | | ||
64K x 16 HIGH-SPEED CMOS STATIC RAM FEATURES IS61C6416AL and IS64C6416AL • High-speed access time: 12 ns, 15ns • Low Active Power: 175 mW (typical) • Low Standby Power: 1 mW (typical) CMOS standby IS62C6416AL and IS65C6416AL • High-speed access time: 35 ns, 45ns • Low Active Power: 50 mW (typical) • Low Standby Power: 100 μ | ISSI 矽成半导体 | | ||
1M x 36, 2M x 18 36 Mb SYNCHRONOUS FLOW-THROUGH STATIC RAM FEATURES • Internal self-timed write cycle • Individual Byte Write Control and Global Write • Clock controlled, registered address, data and control • Burst sequence control using MODE input • Three chip enable option for simple depth expansion and address pipelining • Common data inputs a | ISSI 矽成半导体 | | ||
1M x 36, 2M x 18 36 Mb SYNCHRONOUS FLOW-THROUGH STATIC RAM FEATURES • Internal self-timed write cycle • Individual Byte Write Control and Global Write • Clock controlled, registered address, data and control • Burst sequence control using MODE input • Three chip enable option for simple depth expansion and address pipelining • Common data inputs a | ISSI 矽成半导体 | | ||
1M x 36, 2M x 18 36 Mb SYNCHRONOUS FLOW-THROUGH STATIC RAM FEATURES • Internal self-timed write cycle • Individual Byte Write Control and Global Write • Clock controlled, registered address, data and control • Burst sequence control using MODE input • Three chip enable option for simple depth expansion and address pipelining • Common data inputs a | ISSI 矽成半导体 | | ||
1M x 36, 2M x 18 36 Mb SYNCHRONOUS FLOW-THROUGH STATIC RAM FEATURES • Internal self-timed write cycle • Individual Byte Write Control and Global Write • Clock controlled, registered address, data and control • Burst sequence control using MODE input • Three chip enable option for simple depth expansion and address pipelining • Common data inputs a | ISSI 矽成半导体 | | ||
1M x 36, 2M x 18 36 Mb SYNCHRONOUS FLOW-THROUGH STATIC RAM FEATURES • Internal self-timed write cycle • Individual Byte Write Control and Global Write • Clock controlled, registered address, data and control • Burst sequence control using MODE input • Three chip enable option for simple depth expansion and address pipelining • Common data inputs a | ISSI 矽成半导体 | | ||
1M x 36, 2M x 18 36 Mb SYNCHRONOUS FLOW-THROUGH STATIC RAM FEATURES • Internal self-timed write cycle • Individual Byte Write Control and Global Write • Clock controlled, registered address, data and control • Burst sequence control using MODE input • Three chip enable option for simple depth expansion and address pipelining • Common data inputs a | ISSI 矽成半导体 | | ||
128K x 32, 128K x 36, 256K x 18 4 Mb SYNCHRONOUS FLOW-THROUGH STATIC RAM DESCRIPTION The ISSI IS61(64)LF12832A, IS64VF12832A, IS61(64)LF/VF12836A and IS61(64)LF/VF25618A are high-speed, low-power synchronous static RAMs designed to provide burstable, high-performance memory for communication and networking applications. The IS61(64)LF12832A is organized as 131,072 wor | ISSI 矽成半导体 | | ||
128K x 32, 128K x 36, 256K x 18 4 Mb SYNCHRONOUS FLOW-THROUGH STATIC RAM DESCRIPTION The ISSI IS61(64)LF12832A, IS64VF12832A, IS61(64)LF/VF12836A and IS61(64)LF/VF25618A are high-speed, low-power synchronous static RAMs designed to provide burstable, high-performance memory for communication and networking applications. The IS61(64)LF12832A is organized as 131,072 wor | ISSI 矽成半导体 | | ||
128K x 32, 128K x 36, 256K x 18 4 Mb SYNCHRONOUS FLOW-THROUGH STATIC RAM DESCRIPTION The ISSI IS61(64)LF12832A, IS64VF12832A, IS61(64)LF/VF12836A and IS61(64)LF/VF25618A are high-speed, low-power synchronous static RAMs designed to provide burstable, high-performance memory for communication and networking applications. The IS61(64)LF12832A is organized as 131,072 wor | ISSI 矽成半导体 | | ||
128K x36/32 and 256K x18 4Mb, ECC, SYNCHRONOUS FLOW-THROUGH SRAM FEATURES Internal self-timed write cycle Individual Byte Write Control and Global Write Clock controlled, registered address, data and control Burst sequence control using MODE input Three chip enable option for simple depth expansion and address pipelining Common data inputs an | ISSI 矽成半导体 | | ||
128K x36/32 and 256K x18 4Mb, ECC, SYNCHRONOUS FLOW-THROUGH SRAM FEATURES Internal self-timed write cycle Individual Byte Write Control and Global Write Clock controlled, registered address, data and control Burst sequence control using MODE input Three chip enable option for simple depth expansion and address pipelining Common data inputs an | ISSI 矽成半导体 | | ||
128K x36/32 and 256K x18 4Mb, ECC, SYNCHRONOUS FLOW-THROUGH SRAM FEATURES Internal self-timed write cycle Individual Byte Write Control and Global Write Clock controlled, registered address, data and control Burst sequence control using MODE input Three chip enable option for simple depth expansion and address pipelining Common data inputs an | ISSI 矽成半导体 | | ||
128K x36/32 and 256K x18 4Mb, ECC, SYNCHRONOUS FLOW-THROUGH SRAM FEATURES Internal self-timed write cycle Individual Byte Write Control and Global Write Clock controlled, registered address, data and control Burst sequence control using MODE input Three chip enable option for simple depth expansion and address pipelining Common data inputs an | ISSI 矽成半导体 | | ||
128K x36/32 and 256K x18 4Mb, ECC, SYNCHRONOUS FLOW-THROUGH SRAM FEATURES Internal self-timed write cycle Individual Byte Write Control and Global Write Clock controlled, registered address, data and control Burst sequence control using MODE input Three chip enable option for simple depth expansion and address pipelining Common data inputs an | ISSI 矽成半导体 | | ||
128K x36/32 and 256K x18 4Mb, ECC, SYNCHRONOUS FLOW-THROUGH SRAM FEATURES Internal self-timed write cycle Individual Byte Write Control and Global Write Clock controlled, registered address, data and control Burst sequence control using MODE input Three chip enable option for simple depth expansion and address pipelining Common data inputs an | ISSI 矽成半导体 | | ||
128K x36/32 and 256K x18 4Mb, ECC, SYNCHRONOUS FLOW-THROUGH SRAM FEATURES Internal self-timed write cycle Individual Byte Write Control and Global Write Clock controlled, registered address, data and control Burst sequence control using MODE input Three chip enable option for simple depth expansion and address pipelining Common data inputs an | ISSI 矽成半导体 | | ||
128K x36/32 and 256K x18 4Mb, ECC, SYNCHRONOUS FLOW-THROUGH SRAM FEATURES Internal self-timed write cycle Individual Byte Write Control and Global Write Clock controlled, registered address, data and control Burst sequence control using MODE input Three chip enable option for simple depth expansion and address pipelining Common data inputs an | ISSI 矽成半导体 | | ||
128K x36/32 and 256K x18 4Mb, ECC, SYNCHRONOUS FLOW-THROUGH SRAM FEATURES Internal self-timed write cycle Individual Byte Write Control and Global Write Clock controlled, registered address, data and control Burst sequence control using MODE input Three chip enable option for simple depth expansion and address pipelining Common data inputs an | ISSI 矽成半导体 | | ||
128K x36/32 and 256K x18 4Mb, ECC, SYNCHRONOUS FLOW-THROUGH SRAM FEATURES Internal self-timed write cycle Individual Byte Write Control and Global Write Clock controlled, registered address, data and control Burst sequence control using MODE input Three chip enable option for simple depth expansion and address pipelining Common data inputs an | ISSI 矽成半导体 | | ||
128K x36/32 and 256K x18 4Mb, ECC, SYNCHRONOUS FLOW-THROUGH SRAM FEATURES Internal self-timed write cycle Individual Byte Write Control and Global Write Clock controlled, registered address, data and control Burst sequence control using MODE input Three chip enable option for simple depth expansion and address pipelining Common data inputs an | ISSI 矽成半导体 | | ||
128K x36/32 and 256K x18 4Mb, ECC, SYNCHRONOUS FLOW-THROUGH SRAM FEATURES Internal self-timed write cycle Individual Byte Write Control and Global Write Clock controlled, registered address, data and control Burst sequence control using MODE input Three chip enable option for simple depth expansion and address pipelining Common data inputs an | ISSI 矽成半导体 | | ||
128K x36/32 and 256K x18 4Mb, ECC, SYNCHRONOUS FLOW-THROUGH SRAM FEATURES Internal self-timed write cycle Individual Byte Write Control and Global Write Clock controlled, registered address, data and control Burst sequence control using MODE input Three chip enable option for simple depth expansion and address pipelining Common data inputs an | ISSI 矽成半导体 | | ||
128K x36/32 and 256K x18 4Mb, ECC, SYNCHRONOUS FLOW-THROUGH SRAM FEATURES Internal self-timed write cycle Individual Byte Write Control and Global Write Clock controlled, registered address, data and control Burst sequence control using MODE input Three chip enable option for simple depth expansion and address pipelining Common data inputs an | ISSI 矽成半导体 | | ||
128K x36/32 and 256K x18 4Mb, ECC, SYNCHRONOUS FLOW-THROUGH SRAM FEATURES Internal self-timed write cycle Individual Byte Write Control and Global Write Clock controlled, registered address, data and control Burst sequence control using MODE input Three chip enable option for simple depth expansion and address pipelining Common data inputs an | ISSI 矽成半导体 | | ||
128K x36/32 and 256K x18 4Mb, ECC, SYNCHRONOUS FLOW-THROUGH SRAM FEATURES Internal self-timed write cycle Individual Byte Write Control and Global Write Clock controlled, registered address, data and control Burst sequence control using MODE input Three chip enable option for simple depth expansion and address pipelining Common data inputs an | ISSI 矽成半导体 | | ||
128K x36/32 and 256K x18 4Mb, ECC, SYNCHRONOUS FLOW-THROUGH SRAM FEATURES Internal self-timed write cycle Individual Byte Write Control and Global Write Clock controlled, registered address, data and control Burst sequence control using MODE input Three chip enable option for simple depth expansion and address pipelining Common data inputs an | ISSI 矽成半导体 | | ||
128K x36/32 and 256K x18 4Mb, ECC, SYNCHRONOUS FLOW-THROUGH SRAM FEATURES Internal self-timed write cycle Individual Byte Write Control and Global Write Clock controlled, registered address, data and control Burst sequence control using MODE input Three chip enable option for simple depth expansion and address pipelining Common data inputs an | ISSI 矽成半导体 | | ||
128K x36/32 and 256K x18 4Mb, ECC, SYNCHRONOUS FLOW-THROUGH SRAM FEATURES Internal self-timed write cycle Individual Byte Write Control and Global Write Clock controlled, registered address, data and control Burst sequence control using MODE input Three chip enable option for simple depth expansion and address pipelining Common data inputs an | ISSI 矽成半导体 | | ||
128K x36/32 and 256K x18 4Mb, ECC, SYNCHRONOUS FLOW-THROUGH SRAM FEATURES Internal self-timed write cycle Individual Byte Write Control and Global Write Clock controlled, registered address, data and control Burst sequence control using MODE input Three chip enable option for simple depth expansion and address pipelining Common data inputs an | ISSI 矽成半导体 | | ||
128K x36/32 and 256K x18 4Mb, ECC, SYNCHRONOUS FLOW-THROUGH SRAM FEATURES Internal self-timed write cycle Individual Byte Write Control and Global Write Clock controlled, registered address, data and control Burst sequence control using MODE input Three chip enable option for simple depth expansion and address pipelining Common data inputs an | ISSI 矽成半导体 | | ||
128K x36/32 and 256K x18 4Mb, ECC, SYNCHRONOUS FLOW-THROUGH SRAM FEATURES Internal self-timed write cycle Individual Byte Write Control and Global Write Clock controlled, registered address, data and control Burst sequence control using MODE input Three chip enable option for simple depth expansion and address pipelining Common data inputs an | ISSI 矽成半导体 | | ||
128K x36/32 and 256K x18 4Mb, ECC, SYNCHRONOUS FLOW-THROUGH SRAM FEATURES Internal self-timed write cycle Individual Byte Write Control and Global Write Clock controlled, registered address, data and control Burst sequence control using MODE input Three chip enable option for simple depth expansion and address pipelining Common data inputs an | ISSI 矽成半导体 | | ||
128K x36/32 and 256K x18 4Mb, ECC, SYNCHRONOUS FLOW-THROUGH SRAM FEATURES Internal self-timed write cycle Individual Byte Write Control and Global Write Clock controlled, registered address, data and control Burst sequence control using MODE input Three chip enable option for simple depth expansion and address pipelining Common data inputs an | ISSI 矽成半导体 | | ||
128K x 32, 128K x 36, 256K x 18 4 Mb SYNCHRONOUS FLOW-THROUGH STATIC RAM DESCRIPTION The ISSI IS61(64)LF12832A, IS64VF12832A, IS61(64)LF/VF12836A and IS61(64)LF/VF25618A are high-speed, low-power synchronous static RAMs designed to provide burstable, high-performance memory for communication and networking applications. The IS61(64)LF12832A is organized as 131,072 wor | ISSI 矽成半导体 | | ||
128K x 32, 128K x 36, 256K x 18 4 Mb SYNCHRONOUS FLOW-THROUGH STATIC RAM DESCRIPTION The ISSI IS61(64)LF12832A, IS64VF12832A, IS61(64)LF/VF12836A and IS61(64)LF/VF25618A are high-speed, low-power synchronous static RAMs designed to provide burstable, high-performance memory for communication and networking applications. The IS61(64)LF12832A is organized as 131,072 wor | ISSI 矽成半导体 | | ||
128K x36/32 and 256K x18 4Mb, ECC, SYNCHRONOUS FLOW-THROUGH SRAM FEATURES Internal self-timed write cycle Individual Byte Write Control and Global Write Clock controlled, registered address, data and control Burst sequence control using MODE input Three chip enable option for simple depth expansion and address pipelining Common data inputs an | ISSI 矽成半导体 | | ||
128K x36/32 and 256K x18 4Mb, ECC, SYNCHRONOUS FLOW-THROUGH SRAM FEATURES Internal self-timed write cycle Individual Byte Write Control and Global Write Clock controlled, registered address, data and control Burst sequence control using MODE input Three chip enable option for simple depth expansion and address pipelining Common data inputs an | ISSI 矽成半导体 | | ||
128K x36/32 and 256K x18 4Mb, ECC, SYNCHRONOUS FLOW-THROUGH SRAM FEATURES Internal self-timed write cycle Individual Byte Write Control and Global Write Clock controlled, registered address, data and control Burst sequence control using MODE input Three chip enable option for simple depth expansion and address pipelining Common data inputs an | ISSI 矽成半导体 | | ||
128K x36/32 and 256K x18 4Mb, ECC, SYNCHRONOUS FLOW-THROUGH SRAM FEATURES Internal self-timed write cycle Individual Byte Write Control and Global Write Clock controlled, registered address, data and control Burst sequence control using MODE input Three chip enable option for simple depth expansion and address pipelining Common data inputs an | ISSI 矽成半导体 | | ||
128K x36/32 and 256K x18 4Mb, ECC, SYNCHRONOUS FLOW-THROUGH SRAM FEATURES Internal self-timed write cycle Individual Byte Write Control and Global Write Clock controlled, registered address, data and control Burst sequence control using MODE input Three chip enable option for simple depth expansion and address pipelining Common data inputs an | ISSI 矽成半导体 | | ||
128K x36/32 and 256K x18 4Mb, ECC, SYNCHRONOUS FLOW-THROUGH SRAM FEATURES Internal self-timed write cycle Individual Byte Write Control and Global Write Clock controlled, registered address, data and control Burst sequence control using MODE input Three chip enable option for simple depth expansion and address pipelining Common data inputs an | ISSI 矽成半导体 | | ||
128K x36/32 and 256K x18 4Mb, ECC, SYNCHRONOUS FLOW-THROUGH SRAM FEATURES Internal self-timed write cycle Individual Byte Write Control and Global Write Clock controlled, registered address, data and control Burst sequence control using MODE input Three chip enable option for simple depth expansion and address pipelining Common data inputs an | ISSI 矽成半导体 | | ||
128K x36/32 and 256K x18 4Mb, ECC, SYNCHRONOUS FLOW-THROUGH SRAM FEATURES Internal self-timed write cycle Individual Byte Write Control and Global Write Clock controlled, registered address, data and control Burst sequence control using MODE input Three chip enable option for simple depth expansion and address pipelining Common data inputs an | ISSI 矽成半导体 | | ||
128K x36/32 and 256K x18 4Mb, ECC, SYNCHRONOUS FLOW-THROUGH SRAM FEATURES Internal self-timed write cycle Individual Byte Write Control and Global Write Clock controlled, registered address, data and control Burst sequence control using MODE input Three chip enable option for simple depth expansion and address pipelining Common data inputs an | ISSI 矽成半导体 | | ||
128K x36/32 and 256K x18 4Mb, ECC, SYNCHRONOUS FLOW-THROUGH SRAM FEATURES Internal self-timed write cycle Individual Byte Write Control and Global Write Clock controlled, registered address, data and control Burst sequence control using MODE input Three chip enable option for simple depth expansion and address pipelining Common data inputs an | ISSI 矽成半导体 | | ||
128K x36/32 and 256K x18 4Mb, ECC, SYNCHRONOUS FLOW-THROUGH SRAM FEATURES Internal self-timed write cycle Individual Byte Write Control and Global Write Clock controlled, registered address, data and control Burst sequence control using MODE input Three chip enable option for simple depth expansion and address pipelining Common data inputs an | ISSI 矽成半导体 | | ||
128K x36/32 and 256K x18 4Mb, ECC, SYNCHRONOUS FLOW-THROUGH SRAM FEATURES Internal self-timed write cycle Individual Byte Write Control and Global Write Clock controlled, registered address, data and control Burst sequence control using MODE input Three chip enable option for simple depth expansion and address pipelining Common data inputs an | ISSI 矽成半导体 | | ||
128K x36/32 and 256K x18 4Mb, ECC, SYNCHRONOUS FLOW-THROUGH SRAM FEATURES Internal self-timed write cycle Individual Byte Write Control and Global Write Clock controlled, registered address, data and control Burst sequence control using MODE input Three chip enable option for simple depth expansion and address pipelining Common data inputs an | ISSI 矽成半导体 | |
IS64产品属性
- 类型
描述
- Organization：
128Kx32
- Product Type：
Flowthrough
- VccQ：
2.5V/3.3V
- Speed (MHz)：
133117
- tKQ(ns)：
6.5
- Package Pins：
BGA(119)
- Temperature Grade：
A3
- Status：
Prod
| IC供应商 | 芯片型号 | 品牌 | 批号 | 封装 | 库存 | 备注 | 价格 |
|---|---|---|---|---|---|---|---|
INTERSIL |
23+ |
45800 |
原厂授权一级代理,专业海外优势订货,价格优势、品种 |
||||
ISOCOM |
25+ |
DIPSOP6 |
20000 |
全新原装正品支持含税 |
|||
ISOCOM |
2447 |
DIP-6 |
100500 |
一级代理专营品牌!原装正品,优势现货,长期排单到货 |
|||
ISOCOM |
23+ |
SOP6 |
8000 |
只做原装现货 |
|||
ISOCOM |
23+ |
SOP6 |
7000 |
||||
TI |
05+ |
原厂原装 |
4231 |
只做全新原装真实现货供应 |
|||
ISOCOM |
24+ |
65200 |
|||||
ISOCOM |
23+ |
14+ |
61424 |
##公司主营品牌长期供应100%原装现货可含税提供技术 |
|||
ISSI |
25+ |
TQFP100 |
3850 |
百分百原装正品 真实公司现货库存 本公司只做原装 可 |
|||
ISOCOM |
03+ |
DIP6 |
1170 |
一级代理,专注军工、汽车、医疗、工业、新能源、电力 |
IS64芯片相关品牌
IS64规格书下载地址
IS64参数引脚图相关
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- IS63WV1288DBLL-10TLI
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- IS63WV1024BLL-12TLI
- IS63WV1024BLL-12HLI
- IS63LV1024L-12JL
- IS63LV1024L-10TLI-TR
- IS63LV1024L-10TLI
- IS63LV1024L-10TL
- IS63LV1024L-10KLI
- IS63LV1024L-10JLI
- IS62WV6416DBLL-45TLI
- IS62WV6416BLL-55TLI
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- IS62WV6416BLL-45BI
- IS62WV5128DBLL-45T2LI
- IS62WV5128DBLL-45HLI
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- IS62WV5128BLL-55T2LI
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- IS611X
- IS611
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- IS6015X
IS64数据表相关新闻
IS63WV1024BLL-12TLI
IS63WV1024BLL-12TLI, TSOP, ISSI, 22+
2023-3-9IS64LV51216-12TLA3
进口代理
2022-8-15IS82C55AZ 原装现货
IS82C55AZ 可做含税，支持实单
2021-9-22IS63LV1024L-12JL进口原装深圳现货
进口原装，国产代理，海量库存，产品齐全，货源渠道百分百正品
2020-6-19IS62WV5128BLL-55TLI
IS62WV5128BLL-55TLI，全新原装当天发货或门市自取0755-82732291.
2019-3-18IS916EN
IS916EN 深圳市拓亿芯电子有限公司，本公司具备一般纳税人，可开16点增值税票， 货源渠道保证原厂原装正品IC，诚信为本，薄利多销。
2019-3-6
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