256K x 36, 512K x 18 9 Mb SYNCHRONOUS FLOW-THROUGH STATIC RAM

FEATURES • Internal self-timed write cycle • Individual Byte Write Control and Global Write • Clock controlled, registered address, data and control • Burst sequence control using MODE input • Three chip enable option for simple depth expansion and address pipelining • Common data inputs a

Synchronous SRAM

256K x 36, 512K x 18 9 Mb SYNCHRONOUS FLOW-THROUGH STATIC RAM

FEATURES • Internal self-timed write cycle • Individual Byte Write Control and Global Write • Clock controlled, registered address, data and control • Burst sequence control using MODE input • Three chip enable option for simple depth expansion and address pipelining • Common data inputs a

256K x 36, 512K x 18 9 Mb SYNCHRONOUS FLOW-THROUGH STATIC RAM

FEATURES • Internal self-timed write cycle • Individual Byte Write Control and Global Write • Clock controlled, registered address, data and control • Burst sequence control using MODE input • Three chip enable option for simple depth expansion and address pipelining • Common data inputs a

256K x 36, 512K x 18 9 Mb SYNCHRONOUS FLOW-THROUGH STATIC RAM

FEATURES • Internal self-timed write cycle • Individual Byte Write Control and Global Write • Clock controlled, registered address, data and control • Burst sequence control using MODE input • Three chip enable option for simple depth expansion and address pipelining • Common data inputs a

256K x 36, 512K x 18 9 Mb SYNCHRONOUS FLOW-THROUGH STATIC RAM

FEATURES • Internal self-timed write cycle • Individual Byte Write Control and Global Write • Clock controlled, registered address, data and control • Burst sequence control using MODE input • Three chip enable option for simple depth expansion and address pipelining • Common data inputs a

256K x 36, 512K x 18 9 Mb SYNCHRONOUS FLOW-THROUGH STATIC RAM

FEATURES • Internal self-timed write cycle • Individual Byte Write Control and Global Write • Clock controlled, registered address, data and control • Burst sequence control using MODE input • Three chip enable option for simple depth expansion and address pipelining • Common data inputs a

256K x 36, 512K x 18 9 Mb SYNCHRONOUS FLOW-THROUGH STATIC RAM

FEATURES • Internal self-timed write cycle • Individual Byte Write Control and Global Write • Clock controlled, registered address, data and control • Burst sequence control using MODE input • Three chip enable option for simple depth expansion and address pipelining • Common data inputs a

256K x 36, 512K x 18 9 Mb SYNCHRONOUS FLOW-THROUGH STATIC RAM

FEATURES • Internal self-timed write cycle • Individual Byte Write Control and Global Write • Clock controlled, registered address, data and control • Burst sequence control using MODE input • Three chip enable option for simple depth expansion and address pipelining • Common data inputs a

封装/外壳：100-LQFP 包装：托盘 描述：IC SRAM 9MBIT PARALLEL 100LQFP 集成电路（IC） 存储器

封装/外壳：100-LQFP 包装：托盘 描述：IC SRAM 9MBIT PARALLEL 100LQFP 集成电路（IC） 存储器

256K x 36, 512K x 18 9 Mb SYNCHRONOUS FLOW-THROUGH STATIC RAM

DESCRIPTION The ISSI IS61LF/VF25636A,IS64LF25636AandIS61LF/VF51218A are high-speed, low-power synchronous static RAMs designed to provide burstable, high-performance memory for communication and networking applications. FEATURES • Internal self-timed write cycle • Individual Byte Write Contr

256K x 36, 512K x 18 9 Mb SYNCHRONOUS FLOW-THROUGH STATIC RAM

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