Octal 3-State Noninverting D Flip-Flop High-Performance Silicon-Gate CMOS

The IN74HCT574A is identical in pinout to the LS/ALS574. This device may be used as a level converter for interfacing TTL or NMOS outputs to High-Speed CMOS inputs. Data meeting the setup time is clocked to the outputs with the rising edge of the Clock. The Output Enable input does not affect the

Octal 3-State Noninverting D Flip-Flop High-Performance Silicon-Gate CMOS

The IN74HCT574A is identical in pinout to the LS/ALS574. This device may be used as a level converter for interfacing TTL or NMOS outputs to High-Speed CMOS inputs. Data meeting the setup time is clocked to the outputs with the rising edge of the Clock. The Output Enable input does not affect the

Octal 3-State Noninverting D Flip-Flop High-Performance Silicon-Gate CMOS

Octal 3-State Noninverting D Flip-Flop High-Performance Silicon-Gate CMOS

The IN74HCT574A is identical in pinout to the LS/ALS574. This device may be used as a level converter for interfacing TTL or NMOS outputs to High-Speed CMOS inputs. Data meeting the setup time is clocked to the outputs with the rising edge of the Clock. The Output Enable input does not affect the

Octal 3-State Noninverting D Flip-Flop High-Performance Silicon-Gate CMOS

The IN74HCT574A is identical in pinout to the LS/ALS574. This device may be used as a level converter for interfacing TTL or NMOS outputs to High-Speed CMOS inputs. Data meeting the setup time is clocked to the outputs with the rising edge of the Clock. The Output Enable input does not affect the

Octal 3-State Noninverting D Flip-Flop High-Performance Silicon-Gate CMOS

The IN74HCT574A is identical in pinout to the LS/ALS574. This device may be used as a level converter for interfacing TTL or NMOS outputs to High-Speed CMOS inputs. Data meeting the setup time is clocked to the outputs with the rising edge of the Clock. The Output Enable input does not affect the

Octal 3-State Noninverting D Flip-Flop High-Performance Silicon-Gate CMOS

The IN74HCT574A is identical in pinout to the LS/ALS574. This device may be used as a level converter for interfacing TTL or NMOS outputs to High-Speed CMOS inputs. Data meeting the setup time is clocked to the outputs with the rising edge of the Clock. The Output Enable input does not affect the

Octal 3-State Noninverting D Flip-Flop High-Performance Silicon-Gate CMOS

Octal 3-state noninverting D flip-flop, high-performance silicon-gate CMOS

Octal D-type flip-flop; positive edge-trigger; 3-state

1. General description The 74HC574; 74HCT574 is an 8-bit positive-edge triggered D-type flip-flop with 3-state outputs. The device features a clock (CP) and output enable (OE) inputs. The flip-flops will store the state of their individual D-inputs that meet the set-up and hold time requirement

Octal D-type flip-flop; positive edge-trigger; 3-state

GENERAL DESCRIPTION The 74HC/HCT574 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. FEATURES • 3-state non-inverting outputs for bus oriented applications • 8-bit positive edge-triggere

Octal D-type flip-flop; positive edge-trigger; 3-state

GENERAL DESCRIPTION The 74HC/HCT574 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. FEATURES • 3-state non-inverting outputs for bus oriented applications • 8-bit positive edge-triggere

Octal D-type flip-flop; positive edge-trigger; 3-state

1. General description The 74HC574; 74HCT574 is an 8-bit positive-edge triggered D-type flip-flop with 3-state outputs. The device features a clock (CP) and output enable (OE) inputs. The flip-flops will store the state of their individual D-inputs that meet the set-up and hold time requirement

Octal D-type flip-flop; positive edge-trigger; 3-state

GENERAL DESCRIPTION The 74HC/HCT574 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. FEATURES • 3-state non-inverting outputs for bus oriented applications • 8-bit positive edge-triggere