OCTAL 3-STATE NONINVERTING TRANSPARENT LATCH

OCTAL 3-STATE NONINVERTING TRANSPARENT LATCH High-Speed Silicon-Gate CMOS The IN74ACT373 is identical in pinout to the LS/ALS373, HC/HCT373. The IN74ACT373 may be used as a level converter for interfacing TTL or NMOS outputs to High Speed CMOS inputs. These latches appear transparent to data (i.

Octal 3-State Noninverting Transparent Latch High-Speed Silicon-Gate CMOS

Octal 3-State Noninverting Transparent Latch High-Speed Silicon-Gate CMOS The IN74ACT373 is identical in pinout to the LS/ALS373, HC/HCT373. The IN74ACT373 may be used as a level converter for interfacing TTL or NMOS outputs to High Speed CMOS inputs. These latches appear transparent to data (i.

Octal 3-state noninverting transparent latch high-speed silicon-gate CMOS

OCTAL D-TYPE LATCH WITH 3 STATE OUTPUT NON INVERTING

DESCRIPTION The 74ACT373 is a high-speed CMOS OCTAL D-TYPE LATCH with 3 STATE OUTPUT NON INVERTING fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology. ■ HIGH SPEED: tPD = 6ns (TYP.) at VCC = 5V ■ LOW POWER DISSIPATION: ICC = 4µA(MAX.) at TA=25°C ■ COMPATIBLE

Octal Transparent Latch with 3-STATE Outputs

General Description The AC/ACT373 consists of eight latches with 3-STATE outputs for bus organized system applications. The flip-flops appear transparent to the data when Latch Enable (LE) is HIGH. When LE is LOW, the data that meets the setup time is latched. Data appears on the bus when the Out

Octal Transparent Latch with 3?뭆tate Outputs

The MC74AC373/74ACT373 consists of eight latches with 3–state outputs for bus organized system applications. The flip–flops appear transparent to the data when Latch Enable (LE) is HIGH. When LE is LOW, the data that meets the setup time is latched. Data appears on the bus when the Output Enable (

Octal Transparent Latch with 3-STATE Outputs

General Description The AC/ACT373 consists of eight latches with 3-STATE outputs for bus organized system applications. The flip-flops appear transparent to the data when Latch Enable (LE) is HIGH. When LE is LOW, the data that meets the setup time is latched. Data appears on the bus when the Out

OCTAL D-TYPE LATCH WITH 3 STATE OUTPUTS (NON INVERTED)

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