3.3V CMOS 18-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS

FEATURES: • 0.5 MICRON CMOS Technology • Typical tSK(o) (Output Skew) 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0) • VCC = 3.3V ± 0.3V, Normal Range • VCC = 2.7V to 3.6V, Extended Range • VCC = 2.5V ± 0.2V • CMOS power levels (0.4μ W typ

封装/外壳：56-TFSOP（0.173"，4.40mm 宽） 包装：管件 描述：IC UNIV BUS DVR 18BIT 56TVSOP 集成电路（IC） 通用总线功能

封装/外壳：56-TFSOP（0.173"，4.40mm 宽） 包装：管件 描述：IC UNIV BUS DVR 18BIT 56TVSOP 集成电路（IC） 通用总线功能

Low Voltage 18-Bit Universal Bus Driver with 3.6V Tolerant Inputs and Outputs

General Description The ALVC16835 low voltage 18-bit universal bus driver combines D-type latches and D-type flip-flops to allow data flow in transparent, latched and clocked modes.The 74ALVC16835 is designed for low voltage (1.65V to 3.6V) VCC applications with I/O capability up to 3.6V. The 74A

18-bit registered driver; 3-state

1 General description The 74ALVC16835A is a 18–bit registered driver. Data flow is controlled by active low output enable (OE), active low latch enable (LE) and clock inputs (CP). When LE is LOW, the A to Y data flow is transparent. When LE is HIGH and CP is held at LOW or HIGH, the data is la

18-bit registered driver 3-State

DESCRIPTION The 74ALVC16835A is a 18–bit registered driver. Data flow is controlled by active low output enable (OE), active low latch enable (LE) and clock inputs (CP). When LE is LOW, the A to Y data flow is transparent. When LE is HIGH and CP is held at LOW or HIGH, the data is latched; on

18-bit registered driver 3-State

DESCRIPTION The 74ALVC16835A is a 18–bit registered driver. Data flow is controlled by active low output enable (OE), active low latch enable (LE) and clock inputs (CP). When LE is LOW, the A to Y data flow is transparent. When LE is HIGH and CP is held at LOW or HIGH, the data is latched; on

18-bit registered driver; 3-state

1 General description The 74ALVC16835A is a 18–bit registered driver. Data flow is controlled by active low output enable (OE), active low latch enable (LE) and clock inputs (CP). When LE is LOW, the A to Y data flow is transparent. When LE is HIGH and CP is held at LOW or HIGH, the data is la