型号 功能描述 生产厂家&企业 LOGO 操作
IDT71V65603S150BGI

256K x 36, 512K x 18 3.3V Synchronous ZBT SRAMs

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IDT

256K x 36, 512K x 18 3.3V Synchronous ZBT™ SRAMs ZBT™ Feature 3.3V I/O, Burst Counter Pipelined Outputs

Features ◆ 256K x 36, 512K x 18 memory configurations ◆ Supports high performance system speed - 150MHz (3.8ns Clock-to-Data Access) ◆ ZBTTM Feature - No dead cycles between write and read cycles ◆ Internally synchronized output buffer enable eliminates the need to control OE ◆ Single R/W (

RENESAS

瑞萨

256K x 36, 512K x 18 3.3V Synchronous ZBT™ SRAMs ZBT™ Feature 3.3V I/O, Burst Counter Pipelined Outputs

Features ◆ 256K x 36, 512K x 18 memory configurations ◆ Supports high performance system speed - 150MHz (3.8ns Clock-to-Data Access) ◆ ZBTTM Feature - No dead cycles between write and read cycles ◆ Internally synchronized output buffer enable eliminates the need to control OE ◆ Single R/W (

RENESAS

瑞萨

256K x 36, 512K x 18 3.3V Synchronous ZBT™ SRAMs ZBT™ Feature 3.3V I/O, Burst Counter Pipelined Outputs

Features ◆ 256K x 36, 512K x 18 memory configurations ◆ Supports high performance system speed - 150MHz (3.8ns Clock-to-Data Access) ◆ ZBTTM Feature - No dead cycles between write and read cycles ◆ Internally synchronized output buffer enable eliminates the need to control OE ◆ Single R/W (

RENESAS

瑞萨

256K x 36, 512K x 18 3.3V Synchronous ZBT™ SRAMs ZBT™ Feature 3.3V I/O, Burst Counter Pipelined Outputs

Features ◆ 256K x 36, 512K x 18 memory configurations ◆ Supports high performance system speed - 150MHz (3.8ns Clock-to-Data Access) ◆ ZBTTM Feature - No dead cycles between write and read cycles ◆ Internally synchronized output buffer enable eliminates the need to control OE ◆ Single R/W (

RENESAS

瑞萨

256K x 36, 512K x 18 3.3V Synchronous ZBT™ SRAMs ZBT™ Feature 3.3V I/O, Burst Counter Pipelined Outputs

Features ◆ 256K x 36, 512K x 18 memory configurations ◆ Supports high performance system speed - 150MHz (3.8ns Clock-to-Data Access) ◆ ZBTTM Feature - No dead cycles between write and read cycles ◆ Internally synchronized output buffer enable eliminates the need to control OE ◆ Single R/W (

RENESAS

瑞萨

更新时间:2025-8-18 16:53:00
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