2.5V ZERO DELAY CLOCK MULTIPLIER, SPREAD SPECTRUM COMPATIBLE

FEATURES: • Phase-Lock Loop Clock Distribution for Applications ranging from 10MHz to 133MHz operating frequency • Distributes one clock input to two banks of four outputs • Separate output enable for each output bank • External feedback (FBK) pin is used to synchronize the outputs to the cl

2.5V ZERO DELAY CLOCK MULTIPLIER, SPREAD SPECTRUM COMPATIBLE

文件：51.1 Kbytes Page：6 Pages

3.3V ZERO DELAY CLOCK MULTIPLIER, SPREAD SPECTRUM COMPATIBLE

FEATURES: • Phase-Lock Loop Clock Distribution for Applications ranging from 10MHz to 133MHz operating frequency • Distributes one clock input to two banks of four outputs • Separate output enable for each output bank • External feedback (FBK) pin is used to synchronize the outputs to the cl

3.3V ZERO DELAY CLOCK MULTIPLIER, SPREAD SPECTRUM COMPATIBLE

文件：60.68 Kbytes Page：10 Pages

2.5V ZERO DELAY CLOCK MULTIPLIER, SPREAD SPECTRUM COMPATIBLE

文件：51.1 Kbytes Page：6 Pages

2.5V ZERO DELAY CLOCK MULTIPLIER, SPREAD SPECTRUM COMPATIBLE

文件：51.1 Kbytes Page：6 Pages

2.5V ZERO DELAY CLOCK MULTIPLIER, SPREAD SPECTRUM COMPATIBLE

文件：51.1 Kbytes Page：6 Pages

2.5V ZERO DELAY CLOCK MULTIPLIER, SPREAD SPECTRUM COMPATIBLE

文件：51.1 Kbytes Page：6 Pages

2.5V ZERO DELAY CLOCK MULTIPLIER, SPREAD SPECTRUM COMPATIBLE

文件：51.1 Kbytes Page：6 Pages

2.5V ZERO DELAY CLOCK MULTIPLIER, SPREAD SPECTRUM COMPATIBLE

文件：51.1 Kbytes Page：6 Pages

2.5V ZERO DELAY CLOCK MULTIPLIER, SPREAD SPECTRUM COMPATIBLE

文件：51.1 Kbytes Page：6 Pages

2.5V ZERO DELAY CLOCK MULTIPLIER, SPREAD SPECTRUM COMPATIBLE

文件：51.1 Kbytes Page：6 Pages

2.5V ZERO DELAY CLOCK MULTIPLIER, SPREAD SPECTRUM COMPATIBLE

文件：51.1 Kbytes Page：6 Pages

2.5V ZERO DELAY CLOCK MULTIPLIER, SPREAD SPECTRUM COMPATIBLE

文件：51.1 Kbytes Page：6 Pages

3.3V Zero Delay Buffer

Functional Description The CY23S08 is a 3.3V zero delay buffer designed to distribute high speed clocks in PC, workstation, datacom, telecom, and other high performance applications. The part has an on-chip PLL which locks to an input clock presented on the REF pin. The PLL feedback must be driv

3.3V Zero Delay Buffer

文件：264.97 Kbytes Page：10 Pages

3.3V Zero Delay Buffer

文件：382.01 Kbytes Page：10 Pages