3.3V ZERO DELAY CLOCK BUFFER

DESCRIPTION: The IDT2309A is a high-speed phase-lock loop (PLL) clock buffer, designed to address high-speed clock distribution applications. The zero delay is achieved by aligning the phase between the incoming clock and the output clock, operable within the range of 10 to 133MHz. The IDT2309A

封装/外壳：16-SOIC（0.154"，3.90mm 宽） 包装：管件 描述：IC CLK BUFFER ZD HI DRV 16-SOIC 集成电路（IC） 时钟发生器，PLL，频率合成器

封装/外壳：16-SOIC（0.154"，3.90mm 宽） 包装：管件 描述：IC CLK BUFFER ZD HI DRV 16-SOIC 集成电路（IC） 时钟发生器，PLL，频率合成器

3.3V ZERO DELAY CLOCK BUFFER

FEATURES: • Phase-Lock Loop Clock Distribution • 10MHz to 133MHz operating frequency • Distributes one clock input to one bank of five and one bank of four outputs • Separate output enable for each output bank • Output Skew

3.3V ZERO DELAY CLOCK BUFFER

FEATURES: • Phase-Lock Loop Clock Distribution • 10MHz to 133MHz operating frequency • Distributes one clock input to one bank of five and one bank of four outputs • Separate output enable for each output bank • Output Skew

3.3V ZERO DELAY CLOCK BUFFER

FEATURES: • Phase-Lock Loop Clock Distribution • 10MHz to 133MHz operating frequency • Distributes one clock input to one bank of five and one bank of four outputs • Separate output enable for each output bank • Output Skew

3.3V ZERO DELAY CLOCK BUFFER

FEATURES: • Phase-Lock Loop Clock Distribution • 10MHz to 133MHz operating frequency • Distributes one clock input to one bank of five and one bank of four outputs • Separate output enable for each output bank • Output Skew

3.3V ZERO DELAY CLOCK BUFFER

FEATURES: • Phase-Lock Loop Clock Distribution • 10MHz to 133MHz operating frequency • Distributes one clock input to one bank of five and one bank of four outputs • Separate output enable for each output bank • Output Skew