3.3V ZERO DELAY CLOCK BUFFER

DESCRIPTION: The IDT2309 is a high-speed phase-lock loop (PLL) clock buffer, designed to address high-speed clock distribution applications. The zero delay is achieved by aligning the phase between the incoming clock and the output clock, operable within the range of 10 to 133MHz. The IDT2309 is

3.3V ZERO DELAY CLOCK BUFFER Phase-Lock Loop Clock Distribution

文件：125.72 Kbytes Page：10 Pages

封装/外壳：16-TSSOP（0.173"，4.40mm 宽） 包装：管件 描述：IC CLK BUFFER ZD HI DRV 16-TSSOP 集成电路（IC） 时钟发生器，PLL，频率合成器

3.3V ZERO DELAY CLOCK BUFFER

DESCRIPTION: The IDT2309 is a high-speed phase-lock loop (PLL) clock buffer, designed to address high-speed clock distribution applications. The zero delay is achieved by aligning the phase between the incoming clock and the output clock, operable within the range of 10 to 133MHz. The IDT2309 is

3.3V ZERO DELAY CLOCK BUFFER

DESCRIPTION: The IDT2309 is a high-speed phase-lock loop (PLL) clock buffer, designed to address high-speed clock distribution applications. The zero delay is achieved by aligning the phase between the incoming clock and the output clock, operable within the range of 10 to 133MHz. The IDT2309 is

3.3V ZERO DELAY CLOCK BUFFER

DESCRIPTION: The IDT2309 is a high-speed phase-lock loop (PLL) clock buffer, designed to address high-speed clock distribution applications. The zero delay is achieved by aligning the phase between the incoming clock and the output clock, operable within the range of 10 to 133MHz. The IDT2309 is

3.3V ZERO DELAY CLOCK BUFFER Phase-Lock Loop Clock Distribution

文件：125.72 Kbytes Page：10 Pages

3.3V ZERO DELAY CLOCK BUFFER Phase-Lock Loop Clock Distribution

文件：125.72 Kbytes Page：10 Pages

封装/外壳：16-TSSOP（0.173"，4.40mm 宽） 包装：托盘 描述：IC CLK BUFF ZD PLL HIDRV 16TSSOP 集成电路（IC） 时钟发生器，PLL，频率合成器

3.3V ZERO DELAY CLOCK BUFFER Phase-Lock Loop Clock Distribution

文件：125.72 Kbytes Page：10 Pages

3.3V ZERO DELAY CLOCK BUFFER

DESCRIPTION: The IDT2309 is a high-speed phase-lock loop (PLL) clock buffer, designed to address high-speed clock distribution applications. The zero delay is achieved by aligning the phase between the incoming clock and the output clock, operable within the range of 10 to 133MHz. The IDT2309 is

3.3V ZERO DELAY CLOCK BUFFER

DESCRIPTION: The IDT2309 is a high-speed phase-lock loop (PLL) clock buffer, designed to address high-speed clock distribution applications. The zero delay is achieved by aligning the phase between the incoming clock and the output clock, operable within the range of 10 to 133MHz. The IDT2309 is

3.3V ZERO DELAY CLOCK BUFFER

DESCRIPTION: The IDT2309 is a high-speed phase-lock loop (PLL) clock buffer, designed to address high-speed clock distribution applications. The zero delay is achieved by aligning the phase between the incoming clock and the output clock, operable within the range of 10 to 133MHz. The IDT2309 is

3.3V ZERO DELAY CLOCK BUFFER Phase-Lock Loop Clock Distribution

文件：125.72 Kbytes Page：10 Pages

3.3V ZERO DELAY CLOCK BUFFER Phase-Lock Loop Clock Distribution

文件：125.72 Kbytes Page：10 Pages