封装/外壳：16-TSSOP（0.173"，4.40mm 宽） 包装：管件 描述：IC CLOCK MULT ZD HI DRV 16-TSSOP 集成电路（IC） 时钟发生器，PLL，频率合成器

封装/外壳：16-TSSOP（0.173"，4.40mm 宽） 包装：管件 描述：IC CLOCK MULT ZD HI DRV 16-TSSOP 集成电路（IC） 时钟发生器，PLL，频率合成器

3.3 VOLT ZERO DELAY CLOCK MULTIPLIER

Features • Phase-Lock Loop Clock Distribution for Applications ranging from 10MHz to 133MHz operating frequency • Distributes one clock input to two banks of four outputs • Separate output enable for each output bank • External feedback (FBK) pin is used to synchronize the outputs to the clo

3.3 VOLT ZERO DELAY CLOCK MULTIPLIER

Features • Phase-Lock Loop Clock Distribution for Applications ranging from 10MHz to 133MHz operating frequency • Distributes one clock input to two banks of four outputs • Separate output enable for each output bank • External feedback (FBK) pin is used to synchronize the outputs to the clo

3.3 VOLT ZERO DELAY CLOCK MULTIPLIER

Features • Phase-Lock Loop Clock Distribution for Applications ranging from 10MHz to 133MHz operating frequency • Distributes one clock input to two banks of four outputs • Separate output enable for each output bank • External feedback (FBK) pin is used to synchronize the outputs to the clo

3.3 VOLT ZERO DELAY CLOCK MULTIPLIER

Features • Phase-Lock Loop Clock Distribution for Applications ranging from 10MHz to 133MHz operating frequency • Distributes one clock input to two banks of four outputs • Separate output enable for each output bank • External feedback (FBK) pin is used to synchronize the outputs to the clo

3.3 VOLT ZERO DELAY CLOCK MULTIPLIER

Features • Phase-Lock Loop Clock Distribution for Applications ranging from 10MHz to 133MHz operating frequency • Distributes one clock input to two banks of four outputs • Separate output enable for each output bank • External feedback (FBK) pin is used to synchronize the outputs to the clo