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| 型号 | 功能描述 | 生产厂家 企业 | LOGO | 操作 |
|---|---|---|---|---|
ICSSSTUAF32868BHLF | 28-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 Description This 28-bit 1:2 configurable registered buffer is designed for 1.7V to 1.9V VDD operation. All inputs are compatible with the JEDEC standard for SSTL_18, except the chip-select gate-enable (CSGEN), control (C), and reset (RESET) inputs, which are LVCMOS. All outputs are edge-controlle | IDT |   | |
28-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 Features • 28-bit 1:2 registered buffer with parity check functionality • Supports SSTL_18 JEDEC specification on data inputs and outputs • Supports LVCMOS switching levels on CSGEN and RESET inputs • Low voltage operation: VDD = 1.7V to 1.9V • Available in 176-ball LFBGA package | RENESAS 瑞萨 | | ||
28-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 Description This 28-bit 1:2 configurable registered buffer is designed for 1.7V to 1.9V VDD operation. All inputs are compatible with the JEDEC standard for SSTL_18, except the chip-select gate-enable (CSGEN), control (C), and reset (RESET) inputs, which are LVCMOS. All outputs are edge-controlle | IDT | | ||
28-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 CONFIDENTIAL Features • 28-bit 1:2 registered buffer with parity check functionality • Supports SSTL_18 JEDEC specification on data inputs and outputs • Supports LVCMOS switching levels on CSGEN and RESET inputs • Low voltage operation: VDD = 1.7V to 1.9V • Available in 176-ball LFBGA package | RENESAS 瑞萨 | | ||
28-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 CONFIDENTIAL Features • 28-bit 1:2 registered buffer with parity check functionality • Supports SSTL_18 JEDEC specification on data inputs and outputs • Supports LVCMOS switching levels on CSGEN and RESET inputs • Low voltage operation: VDD = 1.7V to 1.9V • Available in 176-ball LFBGA package | RENESAS 瑞萨 | | ||
28-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 Description This 28-bit 1:2 configurable registered buffer is designed for 1.7V to 1.9V VDD operation. All inputs are compatible with the JEDEC standard for SSTL_18, except the chip-select gate-enable (CSGEN), control (C), and reset (RESET) inputs, which are LVCMOS. All outputs are edge-controlle | IDT | | ||
28-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 Description This 28-bit 1:2 configurable registered buffer is designed for 1.7V to 1.9V VDD operation. All inputs are compatible with the JEDEC standard for SSTL_18, except the chip-select gate-enable (CSGEN), control (C), and reset (RESET) inputs, which are LVCMOS. All outputs are edge-controlle | IDT | |
| IC供应商 | 芯片型号 | 品牌 | 批号 | 封装 | 库存 | 备注 | 价格 |
|---|---|---|---|---|---|---|---|
ICSI |
23+ |
QFN |
50000 |
全新原装正品现货,支持订货 |
|||
ICS |
9 |
公司优势库存 热卖中! |
|||||
ICS |
25+ |
TSSOP |
2560 |
绝对原装!现货热卖! |
|||
IDT |
23+ |
BGA |
3000 |
一级代理原厂VIP渠道,专注军工、汽车、医疗、工业、 |
|||
ICS |
07+ |
TSSOP |
308 |
普通 |
|||
INTEGRATEDCI |
05+ |
原厂原装 |
4714 |
只做全新原装真实现货供应 |
|||
ICS |
23+ |
BGA |
783 |
全新原装正品现货,支持订货 |
|||
ICS |
25+ |
QFN56 |
1451 |
全新原装正品支持含税 |
|||
ICS |
24+ |
TSSOP-48 |
5825 |
公司原厂原装现货假一罚十!特价出售!强势库存! |
|||
ICS |
21+ |
BGA96 |
10000 |
原装现货假一罚十 |
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2018-12-28
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