12:2, Differential-to-LVDS Multiplexer

General Description The ICS854S202I is a 12:2 Differential-to-LVDS Clock Multiplexer which can operate up to 3GHz. The ICS854S202I has twelve selectable differential clock inputs, any of which can be independently routed to either of the two LVDS outputs. The CLKx, nCLKx input pairs can accept

12:2, Differential-To-LVDS Multiplexer

General Description The ICS854S202I-01 is a 12:2 Differential-to-LVDS Clock Multiplexer which can operate up to 3GHz. The ICS854S202I-01 has twelve selectable differential clock inputs, any of which can be independently routed to either of the two LVDS outputs. The CLKx, nCLKx input pairs can

LOW SKEW, DUAL, PROGRAMMABLE 1-TO-2 DIFFERENTIALTO-LVDS, LVPECL FANOUT BUFFER

GENERAL DESCRIPTION The ICS854S204I is a low skew, high performance dual, programmable 1-to-2 Differential-to-LVDS, LVPECL Fanout Buffer and a member of the HiPerClockS™family of High Performance Clock Solutions from IDT. The PCLKx, nPCLKx pairs can accept most standard differential input levels.

LOW SKEW, DUAL, PROGRAMMABLE 1-TO-2 DIFFERENTIALTO-LVDS, LVPECL FANOUT BUFFER

GENERAL DESCRIPTION The ICS854S204I is a low skew, high performance dual, programmable 1-to-2 Differential-to-LVDS, LVPECL Fanout Buffer and a member of the HiPerClockS™family of High Performance Clock Solutions from IDT. The PCLKx, nPCLKx pairs can accept most standard differential input levels.

LOW SKEW, DUAL, PROGRAMMABLE 1-TO-2 DIFFERENTIALTO-LVDS, LVPECL FANOUT BUFFER

GENERAL DESCRIPTION The ICS854S204I is a low skew, high performance dual, programmable 1-to-2 Differential-to-LVDS, LVPECL Fanout Buffer and a member of the HiPerClockS™family of High Performance Clock Solutions from IDT. The PCLKx, nPCLKx pairs can accept most standard differential input levels.

LOW SKEW, DUAL, PROGRAMMABLE 1-TO-2 DIFFERENTIALTO-LVDS, LVPECL FANOUT BUFFER

GENERAL DESCRIPTION The ICS854S204I is a low skew, high performance dual, programmable 1-to-2 Differential-to-LVDS, LVPECL Fanout Buffer and a member of the HiPerClockS™family of High Performance Clock Solutions from IDT. The PCLKx, nPCLKx pairs can accept most standard differential input levels.

Low Skew, Dual, Programmable 1-to-2 Differential-to-LVDS, LVPECL Fanout Buffer

Features • Two programmable differential LVDS or LVPECL output banks • Two differential clock input pairs • PCLKx, nPCLKx pairs can accept the following differential input levels: LVDS, LVPECL, SSTL, CML • Maximum output frequency: 3GHz • Translates any single ended input signal to LVDS leve

12:2, DIFFERENTIAL-TO-LVDS MULTIPLEXER

文件：486.86 Kbytes Page：17 Pages

LOW SKEW, DUAL, PROGRAMMABLE 1-TO-2 DIFFERENTIALTO-LVDS, LVPECL FANOUT BUFFER

Low Skew, Dual, Programmable 1-to-2 Differential-to-LVDS, LVPECL Fanout Buffer

文件：1.42533 Mbytes Page：23 Pages

Low Skew, Dual, Programmable 1-to-2 Differential-to-LVDS, LVPECL Fanout Buffer

文件：1.42533 Mbytes Page：23 Pages