1-TO-2, LVCMOS/LVTTL-TODIFFERENTIAL HSTL TRANSLATOR

GENERAL DESCRIPTION The ICS85222-02 is a 1-to-2 LVCMOS / LVTTL-to-Differential HSTL translator and a member of the HiPerClocks™ family of High Performance Clock Solutions from IDT. The ICS85222-02 has one single ended clock input. The single-ended clock input accepts LVCMOS or LVTTL input levels

1-TO-2 LVCMOS / LVTTL-TO DIFFERENTIAL HSTL TRANSLATOR

GENERAL DESCRIPTION The ICS85222-02 is a 1-to-2 LVCMOS / LVTTL-to-Differential HSTL translator and a member of the HiPerClocks™ family of High Performance Clock Solutions from ICS. The ICS85222-02 has one single ended clock input. The single ended clock input accepts LVCMOS or LVTTL input levels

1-TO-2, LVCMOS/LVTTL-TODIFFERENTIAL HSTL TRANSLATOR

GENERAL DESCRIPTION The ICS85222-02 is a 1-to-2 LVCMOS / LVTTL-to-Differential HSTL translator and a member of the HiPerClocks™ family of High Performance Clock Solutions from IDT. The ICS85222-02 has one single ended clock input. The single-ended clock input accepts LVCMOS or LVTTL input levels

1-TO-2 LVCMOS / LVTTL-TO DIFFERENTIAL HSTL TRANSLATOR

GENERAL DESCRIPTION The ICS85222-02 is a 1-to-2 LVCMOS / LVTTL-to-Differential HSTL translator and a member of the HiPerClocks™ family of High Performance Clock Solutions from ICS. The ICS85222-02 has one single ended clock input. The single ended clock input accepts LVCMOS or LVTTL input levels

1-TO-2 LVCMOS / LVTTL-TO DIFFERENTIAL HSTL TRANSLATOR

GENERAL DESCRIPTION The ICS85222-02 is a 1-to-2 LVCMOS / LVTTL-to-Differential HSTL translator and a member of the HiPerClocks™ family of High Performance Clock Solutions from ICS. The ICS85222-02 has one single ended clock input. The single ended clock input accepts LVCMOS or LVTTL input levels

1-TO-2, LVCMOS/LVTTL-TODIFFERENTIAL HSTL TRANSLATOR

GENERAL DESCRIPTION The ICS85222-02 is a 1-to-2 LVCMOS / LVTTL-to-Differential HSTL translator and a member of the HiPerClocks™ family of High Performance Clock Solutions from IDT. The ICS85222-02 has one single ended clock input. The single-ended clock input accepts LVCMOS or LVTTL input levels

1-to-2, LVCMOS/LVTTL-to-Differential HSTL Translator

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