FEATURES SUMMARY

HIGH DENSITY NAND FLASH MEMORIES

- Cost effective solutions for mass storage applications

MULTIPLANE ARCHITECTURE

- Array is split into two independent planes. Parallel

Operations on both planes are available, halving

Program and erase time.

NAND INTERFACE

- x8 or x16 bus width

- Multiplexed address/ Data

- Pinout compatibility for all densities

SUPPLY VOLTAGE

- 3.3V device : VCC = 2.7V to 3.6 V : HY27UV08BG5M

MEMORY CELL ARRAY

- (2K + 64) bytes x 128 pages x 16384 blocks

PAGE SIZE

- x8 device : (2048+64 spare) bytes

: HY27UV08BG5M

BLOCK SIZE

- x8 device : (256K+8K) bytes

PAGE READ / PROGRAM

- Random access: 50us (Max)

- Sequentiall access: 25ns (Min)

- Page program time: 800us (Typ)

FAST BLOCK ERASE

- Block erase time: 2.5ms (Typ)

- Multi-Plane block erase time (2blocks) : 2.5ms(Typ)

STATUS REGISTER

ELECTRONIC SIGNATURE

- 1st cycle: Manufacturer Code

- 2nd cycle: Device Code

- 3rd cycle: Internal chip number, Cell Type, Number of

Simultaneously Programmed Pages.

- 4th cycle: Page size, Block size, Organization, Spare

size

- 5th cycle: Multiplane information

CHIP ENABLE DON’T CARE

-Simple interface with microcontroller

HARDWARE DATA PROTECTION

- Program/Erase locked during Power transitions.

DATA RETENTION

- 10000 Program / Erase cycles (with 4bit/528byte ECC)

- 10 Years Data Retention

PACKAGE

- HY27UV08BG(5/F)M-T(P)

: 48-pin TSOP1(12 x 20 x 1.2 mm)

- HY27UV08BG(5/F)M-T (Lead)

- HY27UV08BG(5/F)M-TP (Lead Free)

- HY27UV08BGDM-MP

: 52-TLGA (12 x 17 x 1.0)

- HY27UV08BGDM-MP (Lead Free)