FEATURES SUMMARY

HIGH DENSITY NAND FLASH MEMORIES

- Cost effective solutions for mass storage applications

MULTIPLANE ARCHITECTURE

- Array is split into two independent planes. Parallel Operations on both planes are available, halving

Program and erase time.

NAND INTERFACE

- x8/x16 bus width.

- Address/ Data Multiplexing

- Pinout compatiblity for all densities

SUPPLY VOLTAGE

- 3.3V device : Vcc = 2.7 V ~3.6 V

MEMORY CELL ARRAY

- x8 : (2K + 64) bytes x 64 pages x 2048 blocks

- x16 : (1K + 32) words x 64 pages x 2048 blocks

PAGE SIZE

- (2K + 64 spare) Bytes

- (1K + 32 spare) Words

BLOCK SIZE

- (128K + 4Kspare) Bytes

- (64K + 2Kspare) Words

PAGE READ / PROGRAM

- Random access : 25us (max.)

- Sequential access : 25ns (min.)

- Page program time : 200us (typ.)

- Multi-page program time (2 pages) : 200us (typ.)

COPY BACK PROGRAM

- Automatic block download without latency time

FAST BLOCK ERASE

- Block erase time: 1.5ms (typ.)

- Multi-block erase time (2 blocks) : 1.5ms (typ.)

CACHE READ

- Internal (2048 + 64) Byte buffer to improve the read throughtput.