Product Feature

■ Multi Level Cell (MLC) Technology

■ Power Supply Voltage

- VCC / VCCq= 2.7V ~ 3.6V

■ Organization

- Page Size : 8192 + 640(Spare) bytes

- Block Size : 2M + 160K bytes, 256pages

- Plane Size : 2048 + 42(Extended) blocks

- Device Size : 4096 + 84(Extended) blocks

■ Page Read Time

- Random Read Time (tR) : 60/80us(Typ./Max)

- Sequential Access (tRC/tWC) : 16ns(Min.)

■ Page Write Time

- Page Program Time : 1500(Typ.)

■ Block Erase Time

- Block Erase Time : 5.0ms(Typ.)

■ Hardware Data Protection

- Program/Erase locked during power transitions

■ Package

- Package type : TSOP

- Chip count : SDP

- Pin count : 48

- Size : 12mm x 20mm x 1.2mm

■ Electronic Signature

- 1

st cycle : Manufacturer code

- 2

nd cycle : Device code

- 3

rd cycle : Internal chip number, Cell type,

Number of simultaneously programmed pages

- 4

th cycle : Page size, Block size, Organization,

Spare size

- 5

th cycle : Multi-plane information

- 6

th cycle : Technology, EDO, Interface

■ Reliability

- TBD