12-stage binary counter

DESCRIPTION The HEF4040B is a 12-stage binary ripple counter with a clock input (CP), an overriding asynchronous master reset input (MR) and twelve fully buffered outputs (O0 to O11). The counter advances on the HIGH to LOW transition of CP. A HIGH on MR clears all counter stages and forces all

12-stage binary ripple counter

1. General description The HEF4040B is a 12-stage binary ripple counter with a clock input (CP), an overriding asynchronous master reset input (MR) and twelve fully buffered outputs (Q0 to Q11). The counter advances on the HIGH-to-LOW transition of CP. A HIGH on MR clears all counter stages and

12-stage binary ripple counter

1. General description The HEF4040B is a 12-stage binary ripple counter with a clock input (CP), an overriding asynchronous master reset input (MR) and twelve fully buffered outputs (Q0 to Q11). The counter advances on the HIGH-to-LOW transition of CP. A HIGH on MR clears all counter stages and

封装/外壳：16-SOIC（0.154"，3.90mm 宽） 包装：管件 描述：IC COUNTER BINARY 12STAGE 16SOIC 集成电路（IC） 计数器，除法器

12-stage binary ripple counter

文件：680.54 Kbytes Page：13 Pages

封装/外壳：16-SOIC（0.154"，3.90mm 宽） 包装：管件 描述：IC RIPPLE COUNTER 12ST 16SOIC 集成电路（IC） 计数器，除法器

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