4-bit synchronous binary counter with synchronous reset

DESCRIPTION The HEF40163B is a fully synchronous edge-triggered 4-bit binary counter with a clock input (CP), four synchronous parallel data inputs (P0 to P3), four synchronous mode control inputs (parallel enable (PE), count enable parallel (CEP), count enable trickle (CET) and synchronous reset

4-bit synchronous binary counter with synchronous reset

DESCRIPTION The HEF40163B is a fully synchronous edge-triggered 4-bit binary counter with a clock input (CP), four synchronous parallel data inputs (P0 to P3), four synchronous mode control inputs (parallel enable (PE), count enable parallel (CEP), count enable trickle (CET) and synchronous reset

4-bit synchronous binary counter with synchronous reset

DESCRIPTION The HEF40163B is a fully synchronous edge-triggered 4-bit binary counter with a clock input (CP), four synchronous parallel data inputs (P0 to P3), four synchronous mode control inputs (parallel enable (PE), count enable parallel (CEP), count enable trickle (CET) and synchronous reset

4-bit synchronous binary counter with synchronous reset

DESCRIPTION The HEF40163B is a fully synchronous edge-triggered 4-bit binary counter with a clock input (CP), four synchronous parallel data inputs (P0 to P3), four synchronous mode control inputs (parallel enable (PE), count enable parallel (CEP), count enable trickle (CET) and synchronous reset

4-bit synchronous binary counter with synchronous reset

DESCRIPTION The HEF40163B is a fully synchronous edge-triggered 4-bit binary counter with a clock input (CP), four synchronous parallel data inputs (P0 to P3), four synchronous mode control inputs (parallel enable (PE), count enable parallel (CEP), count enable trickle (CET) and synchronous reset

4-bit synchronous binary counter with synchronous reset

DESCRIPTION The HEF40163B is a fully synchronous edge-triggered 4-bit binary counter with a clock input (CP), four synchronous parallel data inputs (P0 to P3), four synchronous mode control inputs (parallel enable (PE), count enable parallel (CEP), count enable trickle (CET) and synchronous reset

4-bit synchronous binary counter with synchronous reset

DESCRIPTION The HEF40163B is a fully synchronous edge-triggered 4-bit binary counter with a clock input (CP), four synchronous parallel data inputs (P0 to P3), four synchronous mode control inputs (parallel enable (PE), count enable parallel (CEP), count enable trickle (CET) and synchronous reset

4-bit synchronous binary counter with synchronous reset

4-bit synchronous binary counter with synchronous reset

CMOS Synchronous Programmable 4-Bit Counters

CMOS Synchronous Programmable 4-Bit Counters CD40160BMS, CD40161BMS, CD40162BMS and CD40163BMS are 4-bit synchronous programmable counters. The CLEAR function of the CD40162BMS and CD40163BMS is synchronous and a low level at the CLEAR input sets all four outputs low on the next positive CLOCK

CMOS Synchronous Programmable 4-Bit Counters

Features: Internal look-ahead for fast counting Carry output for cascading Synchronously programmable Clear asynchronous input {CD40160B, CD40161B) Clear synchronous input (CD40162B, CD40163B) Synchronous load control input Bm Low-power TTL compatibility m Standardized, symmetrical

Decade Counter with Asynchronous Clear

文件：150.85 Kbytes Page：8 Pages

CMOS Synchronous Programmable 4-Bit Counters

文件：552.41 Kbytes Page：13 Pages

CMOS Synchronous Programmable 4-Bit Counters

文件：958.23 Kbytes Page：17 Pages

Decade Counter with Asynchronous Clear

Decade Counter with Asynchronous Clear

Decade Counter with Asynchronous Clear

SYNCHRONOUS PROGRAMMABLE 4-BIT COUNTERS

SYNCHRONOUS PROGRAMMABLE 4-BIT COUNTERS

C2MOS DIGITAL INTERGRATED CIRCUIT SILICON MONOLITHIC