Dual D-type flip-flop

DESCRIPTION The HEF4013B is a dual D-type flip-flop which features independent set direct (SD), clear direct (CD), clock inputs (CP) and outputs (O, O). Data is accepted when CP is LOW and transferred to the output on the positive-going edge of the clock. The active HIGH asynchronous clear-direct

Dual D-type flip-flop

1. General description The HEF4013B is a dual D-type flip-flop with set and reset; positive-edge trigger. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VDD. Schmitt-trigger action on the clock input makes the circuit

Dual D-type flip-flop

The HEF4013B is a dual D-type flip-flop that features independent set-direct input (SD), clear-direct input (CD), clock input (CP) and outputs (Q, Q). Data is accepted when CP is LOW and is transferred to the output on the positive-going edge of the clock. The active HIGH asynchronous CD and SD inpu • Tolerant of slow clock rise and fall times\n• Fully static operation\n• 5 V, 10 V, and 15 V parametric ratings\n• Standardized symmetrical output characteristics\n• Specified from -40 °C to +125 °C\n• Complies with JEDEC standard JESD 13-B;

Tolerant of slow clock rise and fall times

Tolerant of slow clock rise and fall times

Dual D-type flip-flop

DESCRIPTION The HEF4013B is a dual D-type flip-flop which features independent set direct (SD), clear direct (CD), clock inputs (CP) and outputs (O, O). Data is accepted when CP is LOW and transferred to the output on the positive-going edge of the clock. The active HIGH asynchronous clear-direct

Dual D-type flip-flop

1. General description The HEF4013B is a dual D-type flip-flop with set and reset; positive-edge trigger. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VDD. Schmitt-trigger action on the clock input makes the circuit

Dual D-type flip-flop

The HEF4013B is a dual D-type flip-flop that features independent set-direct input (SD), clear-direct input (CD), clock input (CP) and outputs (Q, Q). Data is accepted when CP is LOW and is transferred to the output on the positive-going edge of the clock. The active HIGH asynchronous CD and SD inpu • Tolerant of slow clock rise and fall times\n• Fully static operation\n• 5 V, 10 V, and 15 V parametric ratings\n• Standardized symmetrical output characteristics\n• Specified from -40 °C to +125 °C\n• Complies with JEDEC standard JESD 13-B;

封装/外壳：14-SOIC（0.154"，3.90mm 宽） 功能：设置（预设）和复位 包装：卷带（TR）剪切带（CT）Digi-Reel® 得捷定制卷带 描述：IC FF D-TYPE DUAL 1BIT 14SO 集成电路（IC） 触发器

Tolerant of slow clock rise and fall times

Dual D-type flip-flop

文件：770.97 Kbytes Page：17 Pages

Standardized symmetrical output characteristics

文件：129.83 Kbytes Page：16 Pages

Dual D-type flip-flop

Standardized symmetrical output characteristics

文件：129.83 Kbytes Page：16 Pages

封装/外壳：14-SOIC（0.154"，3.90mm 宽） 功能：设置（预设）和复位 包装：卷带（TR）剪切带（CT）Digi-Reel® 得捷定制卷带 描述：IC FF D-TYPE DUAL 1BIT 14SO 集成电路（IC） 触发器

Tolerant of slow clock rise and fall times

Tolerant of slow clock rise and fall times

Standardized symmetrical output characteristics

文件：129.83 Kbytes Page：16 Pages

Dual D-type flip-flop

文件：770.97 Kbytes Page：17 Pages

Dual D Flip-Flop

文件：141.41 Kbytes Page：6 Pages

Dual D Flip-Flop

文件：141.41 Kbytes Page：6 Pages

Dual D Flip-Flop

文件：141.41 Kbytes Page：6 Pages

Dual D Flip-Flop

文件：141.41 Kbytes Page：6 Pages

Dual D Flip-Flop

文件：141.41 Kbytes Page：6 Pages