Octal D-type Transparent Latches with 3-state Outputs

Description The HD74LVC373A has eight D type latches with three state outputs in a 20 pin package. When the latch enable input is high, the Q outputs will follow the D inputs. When the latch enable goes low, data at the D inputs will be retained at the outputs until latch enable returns high agai

OCTAL D-TYPE LATCH HIGH PERFORMANCE

DESCRIPTION The 74LVC373A is a low voltage CMOS OCTAL D-TYPE LATCH fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology. It is ideal for 1.65 to 3.6 VCC operations and low power and low noise applications. ■ 5V TOLERANT INPUTS ■ HIGH SPEED: tPD = 6.8ns (MAX.) a

Octal D-type transparent latch with 5-volt tolerant inputs/outputs 3-State

DESCRIPTION The 74LVC373A is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families. Inputs can be driven from either 3.3V or 5V devices. In 3-State operation, outputs can handle 5V. This feature allows the use of these devices as t

Octal D-type transparent latch with 5 V tolerant inputs/outputs; 3-state

1. General description The 74LVC373A is an octal D-type transparent latch with 3-state outputs. The device features latch enable (LE) and output enable (OE) inputs. When LE is HIGH, data at the inputs enter the latches. In this condition the latches are transparent, a latch output will change e

Low-Voltage CMOS Octal Buffer

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OCTAL TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS

文件：473.79 Kbytes Page：10 Pages