Quad. Bistable Latches

Description This latch is ideally suited for use as temporary storage for binary information processing, input/output, and indicator units. Information present at the data (D) input is transferred to the Q output when the latch enable (LE) is high. The Q output will follow the data input as long

Quad bistable transparant latch

Quad bistable transparant latch

1. General description The 74HC75 is a quad bistable transparent latch with complementary outputs. Two latches are simultaneously controlled by one of two active HIGH enable inputs (LE12 and LE34). When LEnn is HIGH, the data enters the latches and appears at the nQ outputs. The nQ outputs foll

Quad bistable transparant latch

Features n Complementary Q and Q outputs n VCC and GND on the center pins n Low-power dissipation n Complies with JEDEC standard no. 7A n ESD protection: u HBM EIA/JESD22-A114-B exceeds 2000 V u MM EIA/JESD22-A115-A exceeds 200 V. n Multiple package options n Specified from -40 °C to +80

Quad bistable transparent latch

General description The 74HC75 is a high-speed Si-gate CMOS device and is pin compatible with low power Schottky TTL (LSTTL). The 74HC75 is specified in compliance with JEDEC standard no. 7A. The 74HC75 has four bistable latches. The two latches are simultaneously controlled by one of two active

Quad bistable transparent latch

General description The 74HC75 is a high-speed Si-gate CMOS device and is pin compatible with low power Schottky TTL (LSTTL). The 74HC75 is specified in compliance with JEDEC standard no. 7A. The 74HC75 has four bistable latches. The two latches are simultaneously controlled by one of two active