Dual Decade Counters

Description The HD74HC390 incorporate dual decade counters, each composed of a divide-by-two and a divide-byfive counter. The divide-by-two and divide-by-five counters can be cascaded to form dual decade, dual biquinary, or various combinations up to a single divide-by-100 counter. Features • H

Dual Decade Counters

Description The HD74HC390 incorporate dual decade counters, each composed of a divide-by-two and a divide-by-five counter. The divide-by-two and divide-by-five counters can be cascaded to form dual decade, dual bi-quinary, or various combinations up to a single divide-by-100 counter. The HD74HC3

Dual Decade Counters

Standard IC>General-Purpose Logics>HD74HC Series

Dual Decade Counters

Description The HD74HC390 incorporate dual decade counters, each composed of a divide-by-two and a divide-by-five counter. The divide-by-two and divide-by-five counters can be cascaded to form dual decade, dual bi-quinary, or various combinations up to a single divide-by-100 counter. The HD74HC3

Dual Decade Counters

Dual decade ripple counter

1. General description The 74HC390; 74HCT390 is a dual 4-bit decade ripple counter divided into four separately clocked sections. The counters have two divide-by-2 sections and two divide-by-5 sections. These sections share an asynchronous master reset input (nMR) and can be used in a BCD decad

DUAL DECADE RIPPLE COUNTER

DUAL DECADE RIPPLE COUNTER

Dual decade ripple counter

GENERAL DESCRIPTION The 74HC/HCT390 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. FEATURES • Two BCD decade or bi-quinary counters • One package can be configured to divide-

Dual decade ripple counter

GENERAL DESCRIPTION The 74HC/HCT390 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. FEATURES • Two BCD decade or bi-quinary counters • One package can be configured to divide-

High?밣erformance Silicon?밎ate CMOS

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