Dual Retriggerable Monostable Multivibrators (with Clear)

Description This multivibrator features both a negative, A, and a positive, B, transition triggered input, either of which can be used as an inhibit input. Also included is a clear input that when taken low resets the one shot. The HD74HC123A can be triggered on the positive transition of the c

Dual Retriggerable Monostable Multivibrators (with Clear)

Description This multivibrator features both a negative, A, and a positive, B, transition triggered input, either of which can be used as an inhibit input. Also included is a clear input that when taken low resets the one shot. The HD74HC123A can be triggered on the positive transition of the c

Old Company Name in Catalogs and Other Documents

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Dual Retriggerable Monostable Multivibrators (with Clear)

Dual Retriggerable Monostable Multivibrators (with Clear)

文件：122.64 Kbytes Page：11 Pages

General-Purpose Logics-HD/RD74HC Series

Dual Retriggerable Monostable Multivibrators (with Clear)

文件：122.64 Kbytes Page：11 Pages

General-Purpose Logics-HD/RD74HC Series

Dual Retriggerable Monostable Multivibrators (with Clear)

文件：122.64 Kbytes Page：11 Pages

Dual retriggerable monostable multivibrator with reset

GENERAL DESCRIPTION The 74HC/HCT123 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. FEATURES • DC triggered from active HIGH or active LOW inputs • Retriggerable for very long

Dual retriggerable monostable multivibrator with reset

1. General description The 74HC123; 74HCT123 is a dual retriggerable monostable multivibrator with reset. The basic output pulse width is programmed by selection of external components (REXT and CEXT). Once triggered this basic pulse width may be extended by retriggering either of the edge trig

Dual retriggerable monostable multivibrator with reset

Dual retriggerable monostable multivibrator with reset

GENERAL DESCRIPTION The 74HC/HCT123 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. FEATURES • DC triggered from active HIGH or active LOW inputs • Retriggerable for very long

High Speed CMOS Logic

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