型号 功能描述 生产厂家&企业 LOGO 操作
HD74HC107RPEL

Dual J-K Flip-Flops (with Clear)

Description This flip-flop is edge sensitive to the clock input and change state on the negative going transition of the clock pulse. Each one has independent J, K, clock, and clear inputs and Q and Q outputs. Clear is independent of the clock and accomplished by a low level on the input. Featur

RENESAS

瑞萨

HD74HC107RPEL

Dual J-K Flip-Flops (with Clear)

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RENESAS

瑞萨

Dual JK flip-flop with reset; negative-edge trigger

GENERAL DESCRIPTION The 74HC/HCT107 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT107 are dual negative-edge triggered JK-type flip-flops featuring individual J, K, cloc

Philips

飞利浦

Dual JK flip-flop with reset; negative-edge trigger

1. General description The 74HC107; 74HCT107 is a dual negative edge triggered JK flip-flop featuring individual J and K inputs, clock (CP) and reset (R) inputs and complementary Q and Q outputs. The reset is an asynchronous active LOW input and operates independently of the clock input. The J

NEXPERIANexperia B.V. All rights reserved

安世安世半导体(中国)有限公司

Dual JK flip-flop with reset; negative-edge trigger

1. General description The 74HC107; 74HCT107 is a dual negative edge triggered JK flip-flop featuring individual J and K inputs, clock (CP) and reset (R) inputs and complementary Q and Q outputs. The reset is an asynchronous active LOW input and operates independently of the clock input. The J

NEXPERIANexperia B.V. All rights reserved

安世安世半导体(中国)有限公司

Dual JK flip-flop with reset; negative-edge trigger

GENERAL DESCRIPTION The 74HC/HCT107 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT107 are dual negative-edge triggered JK-type flip-flops featuring individual J, K, cloc

Philips

飞利浦

Dual JK flip-flop with reset; negative-edge trigger

GENERAL DESCRIPTION The 74HC/HCT107 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT107 are dual negative-edge triggered JK-type flip-flops featuring individual J, K, cloc

Philips

飞利浦

更新时间:2025-8-8 12:40:00
IC供应商 芯片型号 品牌 批号 封装 库存 备注 价格
HIT
24+
SOP
3200
绝对原装自家现货!真实库存!欢迎来电!
HIT
94+
SOP16
2145
全新原装进口自己库存优势
TOSHIBA/东芝
24+
NA/
3260
原装现货,当天可交货,原型号开票
HIT
24+
DIP-14
37500
原装正品现货,价格有优势!
8404
1075
公司优势库存 热卖中!
RENESAS/瑞萨
23+
SOP14
3528
一级代理原厂VIP渠道,专注军工、汽车、医疗、工业、
HIT
三年内
1983
只做原装正品
HIT
24+
SOP
2987
只售原装自家现货!诚信经营!欢迎来电!
HIT
23+
DIP
52425
##公司主营品牌长期供应100%原装现货可含税提供技术
HIT
1922+
SOP
10000
公司进口原装特价处理

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