型号 功能描述 生产厂家 企业 LOGO 操作
HD74HC107FPEL

Dual J-K Flip-Flops (with Clear)

Description This flip-flop is edge sensitive to the clock input and change state on the negative going transition of the clock pulse. Each one has independent J, K, clock, and clear inputs and Q and Q outputs. Clear is independent of the clock and accomplished by a low level on the input. Featur

RENESAS

瑞萨

HD74HC107FPEL

Dual J-K Flip-Flops (with Clear)

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RENESAS

瑞萨

Dual JK flip-flop with reset; negative-edge trigger

GENERAL DESCRIPTION The 74HC/HCT107 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT107 are dual negative-edge triggered JK-type flip-flops featuring individual J, K, cloc

Philips

飞利浦

Dual JK flip-flop with reset; negative-edge trigger

1. General description The 74HC107; 74HCT107 is a dual negative edge triggered JK flip-flop featuring individual J and K inputs, clock (CP) and reset (R) inputs and complementary Q and Q outputs. The reset is an asynchronous active LOW input and operates independently of the clock input. The J

NEXPERIA

安世

Dual JK flip-flop with reset; negative-edge trigger

1. General description The 74HC107; 74HCT107 is a dual negative edge triggered JK flip-flop featuring individual J and K inputs, clock (CP) and reset (R) inputs and complementary Q and Q outputs. The reset is an asynchronous active LOW input and operates independently of the clock input. The J

NEXPERIA

安世

Dual JK flip-flop with reset; negative-edge trigger

GENERAL DESCRIPTION The 74HC/HCT107 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT107 are dual negative-edge triggered JK-type flip-flops featuring individual J, K, cloc

Philips

飞利浦

Dual JK flip-flop with reset; negative-edge trigger

GENERAL DESCRIPTION The 74HC/HCT107 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT107 are dual negative-edge triggered JK-type flip-flops featuring individual J, K, cloc

Philips

飞利浦

更新时间:2025-11-4 14:51:00
IC供应商 芯片型号 品牌 批号 封装 库存 备注 价格
RENESAS
25+23+
New
34686
绝对原装正品现货,全新深圳原装进口现货
HIT
23+
SOP
7000
绝对全新原装!100%保质量特价!请放心订购!
HIT
24+
SOP5.2MM
1331
只做原装正品现货 欢迎来电查询15919825718
HIT
97
SOP
192
原装现货海量库存欢迎咨询
HIT
24+
DIP
5000
原装进口现货假一赔十
24+
SOP
102
HIT
1922+
SOP
10000
公司进口原装特价处理
REN
2023+
DIP
8635
一级代理优势现货,全新正品直营店
HIT
25+
SOP
3200
全新原装、诚信经营、公司现货销售
2023+
3000
进口原装现货

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