型号 功能描述 生产厂家&企业 LOGO 操作
HD74HC107FPEL

Dual J-K Flip-Flops (with Clear)

Description This flip-flop is edge sensitive to the clock input and change state on the negative going transition of the clock pulse. Each one has independent J, K, clock, and clear inputs and Q and Q outputs. Clear is independent of the clock and accomplished by a low level on the input. Featur

RENESASRenesas Technology Corp

瑞萨瑞萨科技有限公司

RENESAS
HD74HC107FPEL

Dual J-K Flip-Flops (with Clear)

文件:127.36 Kbytes Page:10 Pages

RENESASRenesas Technology Corp

瑞萨瑞萨科技有限公司

RENESAS

Dual JK flip-flop with reset; negative-edge trigger

GENERAL DESCRIPTION The 74HC/HCT107 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT107 are dual negative-edge triggered JK-type flip-flops featuring individual J, K, cloc

PhilipsPhilips Semiconductors

飞利浦荷兰皇家飞利浦

Dual JK flip-flop with reset; negative-edge trigger

1. General description The 74HC107; 74HCT107 is a dual negative edge triggered JK flip-flop featuring individual J and K inputs, clock (CP) and reset (R) inputs and complementary Q and Q outputs. The reset is an asynchronous active LOW input and operates independently of the clock input. The J

NEXPERIANexperia B.V. All rights reserved

安世安世半导体(中国)有限公司

NEXPERIA

Dual JK flip-flop with reset; negative-edge trigger

1. General description The 74HC107; 74HCT107 is a dual negative edge triggered JK flip-flop featuring individual J and K inputs, clock (CP) and reset (R) inputs and complementary Q and Q outputs. The reset is an asynchronous active LOW input and operates independently of the clock input. The J

NEXPERIANexperia B.V. All rights reserved

安世安世半导体(中国)有限公司

NEXPERIA

Dual JK flip-flop with reset; negative-edge trigger

GENERAL DESCRIPTION The 74HC/HCT107 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT107 are dual negative-edge triggered JK-type flip-flops featuring individual J, K, cloc

PhilipsPhilips Semiconductors

飞利浦荷兰皇家飞利浦

Dual JK flip-flop with reset; negative-edge trigger

GENERAL DESCRIPTION The 74HC/HCT107 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT107 are dual negative-edge triggered JK-type flip-flops featuring individual J, K, cloc

PhilipsPhilips Semiconductors

飞利浦荷兰皇家飞利浦

更新时间:2025-8-6 11:10:00
IC供应商 芯片型号 品牌 批号 封装 库存 备注 价格
RENESAS/瑞萨
23+
SOP14
3528
一级代理原厂VIP渠道,专注军工、汽车、医疗、工业、
HIT
24+
DIP
5000
原装进口现货假一赔十
HIT
24+
SOP
3200
绝对原装自家现货!真实库存!欢迎来电!
HIT
1922+
SOP
10000
公司进口原装特价处理
HIT
23+
SOP5.2mm
48172
##公司主营品牌长期供应100%原装现货可含税提供技术
HITACHI/日立
23+
SOP-0.52-14
50000
全新原装正品现货,支持订货
RENESAS
25+23+
New
34686
绝对原装正品现货,全新深圳原装进口现货
HIT
2020+
DIP
119
百分百原装正品 真实公司现货库存 本公司只做原装 可
24+
SOP
102
HIT
23+
SOP
7000
绝对全新原装!100%保质量特价!请放心订购!

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