20-bit Universal Bus Driver with 3-state Outputs

Description This 20-bit universal bus driver is designed for 2.3 V to 3.6 V VCC operation. Features • VCC = 2.3 V to 3.6 V • Typical VOL ground bounce 2.0 V (@VCC = 3.3 V, Ta = 25°C) • High output current ±12 mA (@VCC = 3.0 V) • A

20-bit Universal Bus Driver with 3-state Outputs

20-bit registered driver with inverted register enable and 30 Ω termination resistors; 3-state

1 General description The 74ALVC162836A is a 20-bit universal bus driver. Data flow is controlled by output enable (OE), latch enable (LE) and clock inputs (CP). When LE is HIGH, the An to Yn data flow is transparent. When LE is HIGH and CP is held at LOW or HIGH, the data is latched; on the L

20-bit registered driver with inverted register enable and 30ohm termination resistors 3-State

DESCRIPTION The 74ALVC162836A is an 20-bit universal bus driver. Data flow is controlled by output enable (OE), latch enable (LE) and clock inputs (CP). When LE is HIGH, the A to Y data flow is transparent. When LE is HIGH and CP is held at LOW or HIGH, the data is latched; on the LOW to HIGH tr

20-bit registered driver with inverted register enable and 30ohm termination resistors 3-State

DESCRIPTION The 74ALVC162836A is an 20-bit universal bus driver. Data flow is controlled by output enable (OE), latch enable (LE) and clock inputs (CP). When LE is HIGH, the A to Y data flow is transparent. When LE is HIGH and CP is held at LOW or HIGH, the data is latched; on the LOW to HIGH tr

20-bit registered driver with inverted register enable and 30ohm termination resistors 3-State

文件：100.32 Kbytes Page：12 Pages

20-bit registered driver with inverted register enable and 30ohm termination resistors 3-State

文件：100.32 Kbytes Page：12 Pages