型号 功能描述 生产厂家&企业 LOGO 操作
H5PS1G63JFR

1Gb DDR2 SDRAM

Key Features • VDD = 1.8 +/- 0.1V • VDDQ = 1.8 +/- 0.1V • All inputs and outputs are compatible with SSTL_18 interface • 8 banks • Fully differential clock inputs (CK, /CK) operation • Double data rate interface • Source synchronous-data transaction aligned to bidirectional data strobe (DQS

Hynix

海力士

1Gb DDR2 SDRAM

Key Features • VDD = 1.8 +/- 0.1V • VDDQ = 1.8 +/- 0.1V • All inputs and outputs are compatible with SSTL_18 interface • 8 banks • Fully differential clock inputs (CK, /CK) operation • Double data rate interface • Source synchronous-data transaction aligned to bidirectional data strobe (DQS

Hynix

海力士

1Gb DDR2 SDRAM

Key Features • VDD = 1.8 +/- 0.1V • VDDQ = 1.8 +/- 0.1V • All inputs and outputs are compatible with SSTL_18 interface • 8 banks • Fully differential clock inputs (CK, /CK) operation • Double data rate interface • Source synchronous-data transaction aligned to bidirectional data strobe (DQS

Hynix

海力士

1Gb DDR2 SDRAM

Key Features • VDD = 1.8 +/- 0.1V • VDDQ = 1.8 +/- 0.1V • All inputs and outputs are compatible with SSTL_18 interface • 8 banks • Fully differential clock inputs (CK, /CK) operation • Double data rate interface • Source synchronous-data transaction aligned to bidirectional data strobe (DQS

Hynix

海力士

1Gb DDR2 SDRAM

Key Features • VDD = 1.8 +/- 0.1V • VDDQ = 1.8 +/- 0.1V • All inputs and outputs are compatible with SSTL_18 interface • 8 banks • Fully differential clock inputs (CK, /CK) operation • Double data rate interface • Source synchronous-data transaction aligned to bidirectional data strobe (DQS

Hynix

海力士

1Gb DDR2 SDRAM

Key Features • VDD = 1.8 +/- 0.1V • VDDQ = 1.8 +/- 0.1V • All inputs and outputs are compatible with SSTL_18 interface • 8 banks • Fully differential clock inputs (CK, /CK) operation • Double data rate interface • Source synchronous-data transaction aligned to bidirectional data strobe (DQS

Hynix

海力士

1Gb DDR2 SDRAM

Key Features • VDD = 1.8 +/- 0.1V • VDDQ = 1.8 +/- 0.1V • All inputs and outputs are compatible with SSTL_18 interface • 8 banks • Fully differential clock inputs (CK, /CK) operation • Double data rate interface • Source synchronous-data transaction aligned to bidirectional data strobe (DQS

Hynix

海力士

1Gb DDR2 SDRAM

Key Features • VDD = 1.8 +/- 0.1V • VDDQ = 1.8 +/- 0.1V • All inputs and outputs are compatible with SSTL_18 interface • 8 banks • Fully differential clock inputs (CK, /CK) operation • Double data rate interface • Source synchronous-data transaction aligned to bidirectional data strobe (DQS

Hynix

海力士

1Gb DDR2 SDRAM

Key Features • VDD = 1.8 +/- 0.1V • VDDQ = 1.8 +/- 0.1V • All inputs and outputs are compatible with SSTL_18 interface • 8 banks • Fully differential clock inputs (CK, /CK) operation • Double data rate interface • Source synchronous-data transaction aligned to bidirectional data strobe (DQS

Hynix

海力士

1Gb DDR2 SDRAM

Key Features • VDD = 1.8 +/- 0.1V • VDDQ = 1.8 +/- 0.1V • All inputs and outputs are compatible with SSTL_18 interface • 8 banks • Fully differential clock inputs (CK, /CK) operation • Double data rate interface • Source synchronous-data transaction aligned to bidirectional data strobe (DQS

Hynix

海力士

1Gb DDR2 SDRAM

Key Features • VDD = 1.8 +/- 0.1V • VDDQ = 1.8 +/- 0.1V • All inputs and outputs are compatible with SSTL_18 interface • 8 banks • Fully differential clock inputs (CK, /CK) operation • Double data rate interface • Source synchronous-data transaction aligned to bidirectional data strobe (DQS

Hynix

海力士

1Gb DDR2 SDRAM

Key Features • VDD = 1.8 +/- 0.1V • VDDQ = 1.8 +/- 0.1V • All inputs and outputs are compatible with SSTL_18 interface • 8 banks • Fully differential clock inputs (CK, /CK) operation • Double data rate interface • Source synchronous-data transaction aligned to bidirectional data strobe (DQS

Hynix

海力士

1Gb DDR2 SDRAM

Key Features • VDD = 1.8 +/- 0.1V • VDDQ = 1.8 +/- 0.1V • All inputs and outputs are compatible with SSTL_18 interface • 8 banks • Fully differential clock inputs (CK, /CK) operation • Double data rate interface • Source synchronous-data transaction aligned to bidirectional data strobe (DQS

Hynix

海力士

1Gb DDR2 SDRAM

Key Features • VDD = 1.8 +/- 0.1V • VDDQ = 1.8 +/- 0.1V • All inputs and outputs are compatible with SSTL_18 interface • 8 banks • Fully differential clock inputs (CK, /CK) operation • Double data rate interface • Source synchronous-data transaction aligned to bidirectional data strobe (DQS

Hynix

海力士

1Gb DDR2 SDRAM

Key Features • VDD = 1.8 +/- 0.1V • VDDQ = 1.8 +/- 0.1V • All inputs and outputs are compatible with SSTL_18 interface • 8 banks • Fully differential clock inputs (CK, /CK) operation • Double data rate interface • Source synchronous-data transaction aligned to bidirectional data strobe (DQS

Hynix

海力士

1Gb DDR2 SDRAM

Key Features • VDD = 1.8 +/- 0.1V • VDDQ = 1.8 +/- 0.1V • All inputs and outputs are compatible with SSTL_18 interface • 8 banks • Fully differential clock inputs (CK, /CK) operation • Double data rate interface • Source synchronous-data transaction aligned to bidirectional data strobe (DQS

Hynix

海力士

1Gb DDR2 SDRAM

Key Features • VDD = 1.8 +/- 0.1V • VDDQ = 1.8 +/- 0.1V • All inputs and outputs are compatible with SSTL_18 interface • 8 banks • Fully differential clock inputs (CK, /CK) operation • Double data rate interface • Source synchronous-data transaction aligned to bidirectional data strobe (DQS

Hynix

海力士

1Gb DDR2 SDRAM

Key Features • VDD = 1.8 +/- 0.1V • VDDQ = 1.8 +/- 0.1V • All inputs and outputs are compatible with SSTL_18 interface • 8 banks • Fully differential clock inputs (CK, /CK) operation • Double data rate interface • Source synchronous-data transaction aligned to bidirectional data strobe (DQS

Hynix

海力士

1Gb DDR2 SDRAM

Key Features • VDD = 1.8 +/- 0.1V • VDDQ = 1.8 +/- 0.1V • All inputs and outputs are compatible with SSTL_18 interface • 8 banks • Fully differential clock inputs (CK, /CK) operation • Double data rate interface • Source synchronous-data transaction aligned to bidirectional data strobe (DQS

Hynix

海力士

1Gb DDR2 SDRAM

Key Features • VDD = 1.8 +/- 0.1V • VDDQ = 1.8 +/- 0.1V • All inputs and outputs are compatible with SSTL_18 interface • 8 banks • Fully differential clock inputs (CK, /CK) operation • Double data rate interface • Source synchronous-data transaction aligned to bidirectional data strobe (DQS

Hynix

海力士

1Gb DDR2 SDRAM

Key Features • VDD = 1.8 +/- 0.1V • VDDQ = 1.8 +/- 0.1V • All inputs and outputs are compatible with SSTL_18 interface • 8 banks • Fully differential clock inputs (CK, /CK) operation • Double data rate interface • Source synchronous-data transaction aligned to bidirectional data strobe (DQS

Hynix

海力士

1Gb DDR2 SDRAM

Key Features • VDD = 1.8 +/- 0.1V • VDDQ = 1.8 +/- 0.1V • All inputs and outputs are compatible with SSTL_18 interface • 8 banks • Fully differential clock inputs (CK, /CK) operation • Double data rate interface • Source synchronous-data transaction aligned to bidirectional data strobe (DQS

Hynix

海力士

1Gb DDR2 SDRAM

Key Features • VDD = 1.8 +/- 0.1V • VDDQ = 1.8 +/- 0.1V • All inputs and outputs are compatible with SSTL_18 interface • 8 banks • Fully differential clock inputs (CK, /CK) operation • Double data rate interface • Source synchronous-data transaction aligned to bidirectional data strobe (DQS

Hynix

海力士

1Gb DDR2 SDRAM

Key Features • VDD = 1.8 +/- 0.1V • VDDQ = 1.8 +/- 0.1V • All inputs and outputs are compatible with SSTL_18 interface • 8 banks • Fully differential clock inputs (CK, /CK) operation • Double data rate interface • Source synchronous-data transaction aligned to bidirectional data strobe (DQS

Hynix

海力士

1Gb DDR2 SDRAM

Key Features • VDD = 1.8 +/- 0.1V • VDDQ = 1.8 +/- 0.1V • All inputs and outputs are compatible with SSTL_18 interface • 8 banks • Fully differential clock inputs (CK, /CK) operation • Double data rate interface • Source synchronous-data transaction aligned to bidirectional data strobe (DQS

Hynix

海力士

海力士原装现货DDR

文件:993.533 Kbytes Page:12 Pages

海力士原装现货DDR

文件:993.533 Kbytes Page:12 Pages

海力士原装现货DDR

文件:993.533 Kbytes Page:12 Pages

1Gb(64Mx16) DDR2 SDRAM

Description Device Features & Ordering Information Key Features • VDD = 1.8 +/- 0.1V • VDDQ = 1.8 +/- 0.1V • All inputs and outputs are compatible with SSTL_18 interface •8 banks • Fully differential clock inputs (CK, /CK) operation • Double data rate interface • Sou

Hynix

海力士

1Gb DDR2 SDRAM

Description Device Features & Ordering Information Key Features • VDD = 1.8 +/- 0.1V • VDDQ = 1.8 +/- 0.1V • All inputs and outputs are compatible with SSTL_18 interface • 8 banks • Fully differential clock inputs (CK, /CK) operation • Double data rate interface • Source synchronous-d

Hynix

海力士

H5PS1G63JFR产品属性

  • 类型

    描述

  • 型号

    H5PS1G63JFR

  • 制造商

    HYNIX

  • 制造商全称

    Hynix Semiconductor

  • 功能描述

    1Gb DDR2 SDRAM

更新时间:2025-8-14 23:23:00
IC供应商 芯片型号 品牌 批号 封装 库存 备注 价格
SKHYNIX
24+
BGA
8000
只做原装正品现货
HYNIX
24+
NA/
6506
原装现货,当天可交货,原型号开票
SKHYNIX
23+
BGA
98900
原厂原装正品现货!!
SK hynix
16+
BGA
580
一级代理,专注军工、汽车、医疗、工业、新能源、电力
SKHYNIX/海力士
25+
FBGA84
12496
SKHYNIX/海力士原装正品H5PS1G63JFR-Y5C即刻询购立享优惠#长期有货
HYNIX/海力士
21+
BGA
9800
只做原装正品假一赔十!正规渠道订货!
SKHYNIX
25+
BGA
13800
原装,请咨询
HYNIX/海力士
25+
BGA
8000
全新原装正品支持含税
HYNIX
14+
BGA
9860
大量原装进口现货,一手货源,一站式服务,可开17%增
HYNIX
1513+
NGA
11784
只做原厂原装,认准宝芯创配单专家

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