LOW NOISE GAIN BLOCK 0.4 to 4.2 GHz

FEATURES Flexible Bias Voltage and Current Process: GaAs pHEMT Compact 1.5 x 1.5 mm DFN-6 Package Tested to AEC-Q100 Grade 2 100 Device Reflow at Assembly 100 Optical Die Inspection Reference: 5 V / 2332.5 MHz / 50 mA Gain: 17.8 dB OIP3: 33 dBm OP1dB: 22.5 dBm Evaluation Board Noise Fig

High Linearity Gain Blocks

Reference: 5V/50 mA/2335.5MHz\n• Gain: 17.8 dB\n• EVB NF: 0.9 dB\n• OP1dB: 21 dBm\n• OIP3: 32 dBm @ +2 dBm POUT/tone \n• Excellent Broadband Performance\n• Incorporates Optimized Tuning for the SDARS Band\n• AEC-Q100 Qualified for Automotive Applications\n• Flexible Biasing Provides Latitude for Lin;

NAND GATES

DESCRIPTION The HCC4011B, HCC4012B and HCC4023B (extended temperature range) and HCF4011B, HCF4012B and HCF4023B (intermediate temperature range) are monolithic, integrated circuit, available in 14-lead dual in-line plastic or ceramic package and plastic micropackage. The HCC/HCF4011B, HCC/HCF40

NAND GATES

DESCRIPTION The HCC4011B, HCC4012B and HCC4023B (extended temperature range) and HCF4011B, HCF4012B and HCF4023B (intermediate temperature range) are monolithic, integrated circuit, available in 14-lead dual in-line plastic or ceramic package and plastic micropackage. The HCC/HCF4011B, HCC/HCF40

Dual 4-input NAND gate

DESCRIPTION The HEF4012B provides the positive dual 4-input NAND function. The outputs are fully buffered for highest noise immunity and pattern insensitivity of output impedance.

Dual 4-input NAND gate

DESCRIPTION The HEF4012B provides the positive dual 4-input NAND function. The outputs are fully buffered for highest noise immunity and pattern insensitivity of output impedance.

Dual 4-input NAND gate

DESCRIPTION The HEF4012B provides the positive dual 4-input NAND function. The outputs are fully buffered for highest noise immunity and pattern insensitivity of output impedance.