Linear Gain Block with Bypass 0.15 to 6 GHz

FEATURES Flexible Bias Voltage and Current Process: GaAs pHEMT Single Control Logic Input Internally Matched to 50 Ω Compact 1.5 x 1.5 mm DFN-6 Package Reference: 5 V / 80 mA / 1.9 GHz Gain: 18.5 dB OP1dB: 22 dBm OIP3: 36 dBm Evaluation Board Noise Figure: 1.8 dB Bypass Mode Gain: -1.5

Broadband LNAs

Reference: 5V/80mA/1.9GHz\n• Gain: 18.4 dB\n• EVB NF: 1.6 dB\n• OIP3: 37.0 dBm\n• OP1dB: 22.0 dBm\n• Bypass Mode Gain: -1.5 dB\n• Bypass OP1dB: 25.0 dBm\n• Bypass OIP3: 46.0 dBm\n• Single Control Logic Input\n• Flexible Bias Voltage and Current\n• Internally Matched to 50 Ω\n• Process: GaAs pHEMT;

UHF power LDMOS transistor

DESCRIPTION Silicon N-channel enhancement mode lateral D-MOS transistor encapsulated in a 2-lead flangeless package (SOT538A) with a ceramic cap. The common source is connected to the mounting base. FEATURES • High power gain • Easy power control • Excellent ruggedness • Source on mounting b

LOW-NOISE DUAL PRE-AMPLIFIER

文件：218.65 Kbytes Page：5 Pages

LOW-NOISE DUAL PRE-AMPLIFIER

文件：218.65 Kbytes Page：5 Pages

LOW-NOISE DUAL PRE-AMPLIFIER

文件：218.65 Kbytes Page：5 Pages

LOW-NOISE DUAL PRE-AMPLIFIER

文件：218.65 Kbytes Page：5 Pages