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GAL20V8

High Performance E2CMOS PLD Generic Array Logic

Description The GAL20V8C, at 5ns maximum propagation delay time, combines a high performance CMOS process with Electrically Erasable (E2) floating gate technology to provide the highest speed performance available in the PLD market. High speed erase times (

LATTICE

莱迪思

GAL20V8

Programmable Logic Devices

LATTICE

莱迪思

High Performance E2CMOS PLD Generic Array Logic

Description The GAL20V8C, at 5ns maximum propagation delay time, combines a high performance CMOS process with Electrically Erasable (E2) floating gate technology to provide the highest speed performance available in the PLD market. High speed erase times (

LATTICE

莱迪思

High Performance E2CMOS PLD Generic Array Logic

Description The GAL20V8C, at 5ns maximum propagation delay time, combines a high performance CMOS process with Electrically Erasable (E2) floating gate technology to provide the highest speed performance available in the PLD market. High speed erase times (

LATTICE

莱迪思

High Performance E2CMOS PLD Generic Array Logic

Description The GAL20V8C, at 5ns maximum propagation delay time, combines a high performance CMOS process with Electrically Erasable (E2) floating gate technology to provide the highest speed performance available in the PLD market. High speed erase times (

LATTICE

莱迪思

High Performance E2CMOS PLD Generic Array Logic

Description The GAL20V8C, at 5ns maximum propagation delay time, combines a high performance CMOS process with Electrically Erasable (E2) floating gate technology to provide the highest speed performance available in the PLD market. High speed erase times (

LATTICE

莱迪思

High Performance E2CMOS PLD Generic Array Logic

Description The GAL20V8C, at 5ns maximum propagation delay time, combines a high performance CMOS process with Electrically Erasable (E2) floating gate technology to provide the highest speed performance available in the PLD market. High speed erase times (

LATTICE

莱迪思

High Performance E2CMOS PLD Generic Array Logic

Description The GAL20V8C, at 5ns maximum propagation delay time, combines a high performance CMOS process with Electrically Erasable (E2) floating gate technology to provide the highest speed performance available in the PLD market. High speed erase times (

LATTICE

莱迪思

High Performance E2CMOS PLD Generic Array Logic

Description The GAL20V8C, at 5ns maximum propagation delay time, combines a high performance CMOS process with Electrically Erasable (E2) floating gate technology to provide the highest speed performance available in the PLD market. High speed erase times (

LATTICE

莱迪思

High Performance E2CMOS PLD Generic Array Logic

Description The GAL20V8C, at 5ns maximum propagation delay time, combines a high performance CMOS process with Electrically Erasable (E2) floating gate technology to provide the highest speed performance available in the PLD market. High speed erase times (

LATTICE

莱迪思

High Performance E2CMOS PLD Generic Array Logic

Description The GAL20V8C, at 5ns maximum propagation delay time, combines a high performance CMOS process with Electrically Erasable (E2) floating gate technology to provide the highest speed performance available in the PLD market. High speed erase times (

LATTICE

莱迪思

High Performance E2CMOS PLD Generic Array Logic

Description The GAL20V8C, at 5ns maximum propagation delay time, combines a high performance CMOS process with Electrically Erasable (E2) floating gate technology to provide the highest speed performance available in the PLD market. High speed erase times (

LATTICE

莱迪思

High Performance E2CMOS PLD Generic Array Logic

Description The GAL20V8C, at 5ns maximum propagation delay time, combines a high performance CMOS process with Electrically Erasable (E2) floating gate technology to provide the highest speed performance available in the PLD market. High speed erase times (

LATTICE

莱迪思

High Performance E2CMOS PLD Generic Array Logic

Description The GAL20V8C, at 5ns maximum propagation delay time, combines a high performance CMOS process with Electrically Erasable (E2) floating gate technology to provide the highest speed performance available in the PLD market. High speed erase times (

LATTICE

莱迪思

High Performance E2CMOS PLD Generic Array Logic

Description The GAL20V8C, at 5ns maximum propagation delay time, combines a high performance CMOS process with Electrically Erasable (E2) floating gate technology to provide the highest speed performance available in the PLD market. High speed erase times (

LATTICE

莱迪思

High Performance E2CMOS PLD Generic Array Logic

Description The GAL20V8C, at 5ns maximum propagation delay time, combines a high performance CMOS process with Electrically Erasable (E2) floating gate technology to provide the highest speed performance available in the PLD market. High speed erase times (

LATTICE

莱迪思

High Performance E2CMOS PLD Generic Array Logic

Description The GAL20V8C, at 5ns maximum propagation delay time, combines a high performance CMOS process with Electrically Erasable (E2) floating gate technology to provide the highest speed performance available in the PLD market. High speed erase times (

LATTICE

莱迪思

High Performance E2CMOS PLD Generic Array Logic

Description The GAL20V8C, at 5ns maximum propagation delay time, combines a high performance CMOS process with Electrically Erasable (E2) floating gate technology to provide the highest speed performance available in the PLD market. High speed erase times (

LATTICE

莱迪思

High Performance E2CMOS PLD Generic Array Logic

Description The GAL20V8C, at 5ns maximum propagation delay time, combines a high performance CMOS process with Electrically Erasable (E2) floating gate technology to provide the highest speed performance available in the PLD market. High speed erase times (

LATTICE

莱迪思

High Performance E2CMOS PLD Generic Array Logic

Description The GAL20V8C, at 5ns maximum propagation delay time, combines a high performance CMOS process with Electrically Erasable (E2) floating gate technology to provide the highest speed performance available in the PLD market. High speed erase times (

LATTICE

莱迪思

High Performance E2CMOS PLD Generic Array Logic

Description The GAL20V8C, at 5ns maximum propagation delay time, combines a high performance CMOS process with Electrically Erasable (E2) floating gate technology to provide the highest speed performance available in the PLD market. High speed erase times (

LATTICE

莱迪思

High Performance E2CMOS PLD Generic Array Logic

Description The GAL20V8C, at 5ns maximum propagation delay time, combines a high performance CMOS process with Electrically Erasable (E2) floating gate technology to provide the highest speed performance available in the PLD market. High speed erase times (

LATTICE

莱迪思

High Performance E2CMOS PLD Generic Array Logic

Description The GAL20V8C, at 5ns maximum propagation delay time, combines a high performance CMOS process with Electrically Erasable (E2) floating gate technology to provide the highest speed performance available in the PLD market. High speed erase times (

LATTICE

莱迪思

High Performance E2CMOS PLD Generic Array Logic

Description The GAL20V8C, at 5ns maximum propagation delay time, combines a high performance CMOS process with Electrically Erasable (E2) floating gate technology to provide the highest speed performance available in the PLD market. High speed erase times (

LATTICE

莱迪思

High Performance E2CMOS PLD Generic Array Logic

Description The GAL20V8C, at 5ns maximum propagation delay time, combines a high performance CMOS process with Electrically Erasable (E2) floating gate technology to provide the highest speed performance available in the PLD market. High speed erase times (

LATTICE

莱迪思

High Performance E2CMOS PLD Generic Array Logic

Description The GAL20V8C, at 5ns maximum propagation delay time, combines a high performance CMOS process with Electrically Erasable (E2) floating gate technology to provide the highest speed performance available in the PLD market. High speed erase times (

LATTICE

莱迪思

High Performance E2CMOS PLD Generic Array Logic

Description The GAL20V8C, at 5ns maximum propagation delay time, combines a high performance CMOS process with Electrically Erasable (E2) floating gate technology to provide the highest speed performance available in the PLD market. High speed erase times (

LATTICE

莱迪思

High Performance E2CMOS PLD Generic Array Logic

Description The GAL20V8C, at 5ns maximum propagation delay time, combines a high performance CMOS process with Electrically Erasable (E2) floating gate technology to provide the highest speed performance available in the PLD market. High speed erase times (

LATTICE

莱迪思

Zero Power E2CMOS PLD

Description\nThe GAL20V8Z and GAL20V8ZD, at 100 µA standby current and 12ns propagation delay provides the highest speed and lowest power combination PLD available in the market. The GAL20V8Z/ZD is manufactured using Lattice Semiconductor's ad vanced zero power E2CMOS process, which combines CMOS wi • ZERO POWER E2CMOS TECHNOLOGY\n   — 100µA Standby Current\n   — Input Transition Detection on GAL20V8Z\n   — Dedicated Power-down Pin on GAL20V8ZD\n   — Input and Output Latching During Power Down\n• HIGH PERFORMANCE E2CMOS TECHNOLOGY\n   — 12 ns Maximum Propagation Delay\n   — Fmax = 83.3 MHz\n   ;

LATTICE

莱迪思

High Performance E2CMOS PLD Generic Array Logic?

文件:582.78 Kbytes Page:25 Pages

LATTICE

莱迪思

Generic Array Logic

TI

德州仪器

Generic Array Logic

文件:601.04 Kbytes Page:16 Pages

NSC

国半

Generic Array Logic

文件:601.04 Kbytes Page:16 Pages

NSC

国半

Generic Array Logic

文件:601.04 Kbytes Page:16 Pages

NSC

国半

Generic Array Logic

文件:601.04 Kbytes Page:16 Pages

NSC

国半

Generic Array Logic

文件:601.04 Kbytes Page:16 Pages

NSC

国半

Generic Array Logic

文件:601.04 Kbytes Page:16 Pages

NSC

国半

Generic Array Logic

文件:601.04 Kbytes Page:16 Pages

NSC

国半

Generic Array Logic

文件:601.04 Kbytes Page:16 Pages

NSC

国半

Generic Array Logic

文件:601.04 Kbytes Page:16 Pages

NSC

国半

Generic Array Logic

文件:601.04 Kbytes Page:16 Pages

NSC

国半

Generic Array Logic

文件:601.04 Kbytes Page:16 Pages

NSC

国半

Generic Array Logic

文件:601.04 Kbytes Page:16 Pages

NSC

国半

Generic Array Logic

文件:601.04 Kbytes Page:16 Pages

NSC

国半

Generic Array Logic

文件:601.04 Kbytes Page:16 Pages

NSC

国半

Generic Array Logic

文件:601.04 Kbytes Page:16 Pages

NSC

国半

Generic Array Logic

文件:601.04 Kbytes Page:16 Pages

NSC

国半

Generic Array Logic

文件:601.04 Kbytes Page:16 Pages

NSC

国半

Generic Array Logic

文件:601.04 Kbytes Page:16 Pages

NSC

国半

Generic Array Logic

文件:601.04 Kbytes Page:16 Pages

NSC

国半

Generic Array Logic

文件:601.04 Kbytes Page:16 Pages

NSC

国半

Generic Array Logic

文件:601.04 Kbytes Page:16 Pages

NSC

国半

Generic Array Logic

文件:601.04 Kbytes Page:16 Pages

NSC

国半

Generic Array Logic

文件:601.04 Kbytes Page:16 Pages

NSC

国半

Generic Array Logic

文件:601.04 Kbytes Page:16 Pages

NSC

国半

Generic Array Logic

文件:601.04 Kbytes Page:16 Pages

NSC

国半

Generic Array Logic

文件:601.04 Kbytes Page:16 Pages

NSC

国半

Generic Array Logic

文件:601.04 Kbytes Page:16 Pages

NSC

国半

Generic Array Logic

文件:601.04 Kbytes Page:16 Pages

NSC

国半

Generic Array Logic

文件:601.04 Kbytes Page:16 Pages

NSC

国半

GAL20V8产品属性

  • 类型

    描述

  • 型号

    GAL20V8

  • 制造商

    LATTICE

  • 制造商全称

    Lattice Semiconductor

  • 功能描述

    High Performance E2CMOS PLD Generic Array Logic

更新时间:2026-5-22 18:00:00
IC供应商 芯片型号 品牌 批号 封装 库存 备注 价格
LAT
23+
5000
原装现货 本公司为一般纳税人,可开17%增值税票原装现
LATTICE/莱迪斯
PLCC28
23+
6000
专业配单原装正品假一罚十
LATTICE/莱迪斯
26+
DIP
9880
只做原装,欢迎来电资询
LATTICE/莱迪斯
24+
PDIP
1155
原装优势现货
LATTICE
21/22+
PLCC
23584
原装正品现货实单价优
LATTICE
24+
SMD
4000
“芯达集团”专营军工百分之百原装进口
Lattice(莱迪斯)
25+
N/A
7786
原装正品现货,原厂订货,可支持含税原型号开票。
LATTICE/莱迪斯
25+
PLCC28
12500
全新原装现货,假一赔十
LATTICE/莱迪斯
2025+
DIP
4709
原装进口价格优 请找坤融电子!
LATTICE31
25+
PLCC
20000
全部原装现货优势产品

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