■ DESCRIPTION

The MB91133/MB91F133, a standard single-chip microcontroller featuring various I/O resources and bus control mechanisms to incorporate the control required for high-performance high-speed CPU processes, is the core unit in the 32-bit RISC CPU (FR family) .

This unit has the optimal specifications for incorporating applications that require high-performance CPU processing power by featuring peripheral I/O resources suitable for single-lens reflex cameras, digital video cameras, etc.

■ FEATURES

1. CPU

• 32-bit RISC (FR30) , load/store architecture, 5-level pipeline

• Multi-purpose register : 32 bits × 16

• 16-bit fixed length instructions (basic instructions) , 1 instruction per cycle

• Instructions for barrel shift, bit processing and inter-memory transfers : Instructions suited to loading purposes

• Function entry / exit instruction, multi load / store instruction of register details : High-level language handling instruction

• Register interlock function : Simplification of assembler description

• Branch instruction with delay slot : Reduction in overheads in case of branching

• Multiplier is built-in / supported at instruction level.

• Signed 32-bit multiplication : 5 cycles

• Signed 16-bit multiplication : 3 cycles

• Interruption (saving PC and PS) : 6 cycles, 16 priority levels

2. Bus Interface

• 24-bit address output, 8/16-bit data input/output

• Basic bus cycle : 2 clock cycles

• Interface support for various memories

• Unused data and address pins can be used as input/output ports.

• Supports “little endian” mode

3. Built-in ROM

Mask device : 254 KB; FLASH device : 254 KB; EVA-FLASH device : 254 KB

4. Built-in RAM

Mask device : 8 KB; FLASH device : 8 KB; EVA-FLASH device : 8 KB

5. DMA Controller

This is a descriptor-type MA controller whose transfer parameters are arranged in the main memory.

A maximum of 8 factors in total (internal and external) can be transferred.

External factors are 3 channels.

6. Bit Search Module

Searches the first “1” / “0” change bit positions within 1 cycle from MSB in 1 word

7. Timer

• 16-bit reload timer × 5 channels

• 16-bit OCU × 8 channels, ICU × 4 channels, free-run timer × 1 channel Output waveform adjusting function for AC motor waveforms is included in the above timer.

• 8/16-bit up/down timer/counter (8-bit × 2 channels or 16-bit × 1 channel) External interruption and pin are shared for AIN and BIN.

• 16-bit down count timer × 5 channels; can also be used as the UART baud rate timer

• 16-bit PPG timer × 6 channels; out-pulse cycle / duty can be changed at random

8. D/A Converter

• 8-bit × 3 channels

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