■ FEATURES

• Power supply voltage of 2.7 V to 3.3 V

• High performance

90 ns maximum access time (Flash)

70 ns maximum access time (SRAM)

• Operating Temperature

–25 °C to +85 °C

• Package 101-ball BGA

— FLASH MEMORY

• Simultaneous Read/Write operations (flex bank)

Two virtual Banks are chosen from the combination of four physical banks

Host system can program or erase in one bank, then read immediately and simultaneously read from the other

bank between read and write operations

Read-while-erase

Read-while-program

• Minimum 100,000 write/erase cycles

• Sector erase architecture

Sixteen 4 K words and one hundred twenty-six 32 K word.

Any combination of sectors can be concurrently erased. Also supports full chip erase.

• Embedded EraseTM* Algorithms

Automatically pre-programs and erases the chip or any sector

• Embedded ProgramTM* Algorithms

Automatically writes and verifies data at specified address

• Data Polling and Toggle Bit feature for detection of program or erase cycle completion

• Ready-Busy output (RY/BY)

Hardware method for detection of program or erase cycle completion

• Automatic sleep mode

When addresses remain stable, automatically switch themselves to low power mode.

• Low VCC write inhibit ≤ 2.5 V

• Hidden ROM (Hi-ROM) region

256 byte of Hi-ROM, accessible through a new “Hi-ROM Enable” command sequence

Factory serialized and protected to provide a secure electronic serial number (ESN)

• WP/ACC input pin

At VIL, allows protection of 2 of 8 Kbytes on both ends of each boot sector, regardless of sector protection/

unprotection status.

At VIH, allows removal of boot sector protection

At VACC, increases program performance

• Program Suspend/Resume

Suspends the program operation to allow a read in another address

• Erase Suspend/Resume

Suspends the erase operation to allow a read in another sector within the same device

• Please refer to “MBM29DL640E” data sheet in detailed function

— SRAM

• Power dissipation

Operating : 50 mA Max.

Standby : 25 µA Max.

• Power down features using CE1s and CE2s

• Data retention supply voltage: 1.5 V to 3.3 V

• CE1s and CE2s Chip Select

• Byte data control: LBs (DQ7-DQ0), UBs (DQ15-DQ8)