■ FEATURES

• Power supply voltage of 2.7 V to 3.3 V

• High performance

90 ns maximum access time (Flash)

85 ns maximum access time (SRAM)

• Operating Temperature

–25°C to +85°C

• Package 71-ball BGA

1.FLASH MEMORY

• Simultaneous Read/Write operations (dual bank)

Multiple devices available with different bank sizes

Host system can program or erase in one bank, then immediately and simultaneously read from the other bank

Zero latency between read and write operations

Read-while-erase

Read-while-program

• Minimum 100,000 write/erase cycles

• Sector erase architecture

Eight 4 K words and sixty three 32 K words.

Any combination of sectors can be concurrently erased. Also supports full chip erase.

• Boot Code Sector Architecture

MB84VD2218X: Top sector

MB84VD2219X: Bottom sector

• Embedded EraseTM Algorithms

Automatically pre-programs and erases the chip or any sector

• Embedded ProgramTM Algorithms

Automatically writes and verifies data at specified address

• Data Polling and Toggle Bit feature for detection of program or erase cycle completion

• Ready-Busy output (RY/BY)

Hardware method for detection of program or erase cycle completion

• Automatic sleep mode

When addresses remain stable, automatically switch themselves to low power mode.

• Low VCCf write inhibit ≤ 2.5 V

• Hidden ROM (Hi-ROM) region

64K byte of Hi-ROM, accessible through a new “Hi-ROM Enable” command sequence

Factory serialized and protected to provide a secure electronic serial number (ESN)

• WP/ACC input pin

At VIL, allows protection of boot sectors, regardless of sector protection/unprotection status

(MB84VD2218XEG/EH:SA69,SA70 MB84VD2219XEG/EH:SA0,SA1)

At VIH, allows removal of boot sector protection

At VACC, program time will reduse by 40.

• Erase Suspend/Resume

Suspends the erase operation to allow a read in another sector within the same device

• Please refer to “MBM29DL32XTE/BE” data sheet in detailed function

2.SRAM

• Power dissipation

Operating : 50 mA max.

Standby : 15 µA max.

• Power down features using CE1s and CE2s

• Data retention supply voltage: 1.5 V to 3.3 V

• CE1s and CE2s Chip Select

• Byte data control: LBs (DQ0 to DQ7), UBs (DQ8 to DQ15)