The Qorivva MPC5645S represents a new generation of 32-bit microcontrollers targeting single-chip automotive instrument cluster applications. MPC5645S devices are part of the MPC56xxS family of Power Architecture®-based devices. This family has been designed with an emphasis on providing cost-effective and high quality graphics capabilities in order to satisfy the increasing market demand for color Thin Film Transistor (TFT) displays within the vehicle cockpit. Traditional cluster functions, such as gauge drive, real time counter, and sound generation are also integrated on each device.

Feature list

• Dual-issue, 32-bit Power Architecture Book E compliant

CPU core complex (e200z4d)

— Memory Management Unit (MMU)

— 4 KB, 2/4-way instruction cache

• 2 MB on-chip ECC flash memory with:

— Flash memory controller

— Prefetch buffers

• 64 KB on-chip ECC SRAM

• 1 MB on-chip non-ECC graphics SRAM with two-port

graphics SRAM controller

• Memory Protection Unit (MPU) with up to 16 region descriptors

and 32-byte region granularity to provide basic

memory access permission and ensure separation

between different codes and data

• Interrupt Controller (INTC) with 181 peripheral

interrupt sources and eight software interrupts

• Two Frequency-Modulated Phase-Locked Loops (FMPLLs)

— Primary FMPLL (FMPLL0) provides a system clock up to 125 MHz

— Auxiliary FMPLL (FMPLL1) is available for use as an alternate,

modulated or non-modulated clock source to

eMIOS modules, QuadSPI and as alternate clock to the DCU

and DCU-Lite for pixel clock generation

• Crossbar switch architecture enables concurrent access of peripherals,

flash memory or RAM from multiple bus

masters

• 16-channel Enhanced Direct Memory Access controller (eDMA)

with multiple transfer request sources using a DMA

channel multiplexer

• Boot Assist Module (BAM) with 8 KB dedicated ROM for embedded

boot code supports boot options including

download of boot code via a serial link (CAN or SCI)

• Two Display Control Units (DCU3 and DCULite) for direct

drive of up to two TFT LCD displays up to XGA

resolution

• Timing Controller (TCON) and RSDS interface for the DCU3 module

• 2D OpenVG 1.1 and raster graphics accelerator (GFX2D)

• Video Input Unit (VIU2) supporting 8/10-bit ITU656

video input, YUV to RGB conversion, video down-scaling,

de-interlacing, contrast adjustment and brightness adjustment.

• DRAM controller supporting DDR1, DDR2, and LPDDR1 DRAMs

• Stepper Motor Controller (SMC)

— High-current drivers for up to six instrument cluster gauges

driven in full dual H-bridge configuration

— Stepper motor return-to-zero and stall detection module

— Stepper motor short circuit detection

• Sound Generator Module (SGM)

— 4-channel mixer

— Supports PCM wave playback and synthesized tones

— Optional PWM or I2S outputs

• Two 16-channel Enhanced Modular Input Output System (eMIOS) modules

— Support a range of 16-bit Input Capture, Output Compare, Pulse

Width Modulation and Quadrature Decode

functions

• 10-bit Analog-to-Digital Converter (ADC)

with a maximum conversion time of 1 μs

— Up to 20 internal channels

— Up to 8 external channels

• Three Deserial Serial Peripheral Interface (DSPI) modules

for full-duplex, synchronous, communications with

external devices

• QuadSPI serial flash memory controller (Continue ...)