General Description

Introduction

The MC68HC908QY4A is a member of the low-cost, high-performance M68HC08 Family of 8-bit microcontroller units (MCUs). All MCUs in the family use the enhanced M68HC08 central processor unit (CPU08) and are available with a variety of modules, memory sizes and types, and package types.

Features

Features include:

• High-performance M68HC08 CPU core

• Fully upward-compatible object code with M68HC05 Family

• 5-V and 3-V operating voltages (VDD)

• 8-MHz internal bus operation at 5 V, 4-MHz at 3 V

• Trimmable internal oscillator

– Software selectable 1 MHz, 2 MHz, or 3.2 MHz internal bus operation

– 8-bit trim capability

– ±25 untrimmed

– Trimmable to approximately 0.4(1)

• Software selectable crystal oscillator range, 32–100 kHz, 1–8 MHz and 8–32 MHz

• Software configurable input clock from either internal or external source

• Auto wakeup from STOP capability using dedicated internal 32-kHz RC or bus clock source

• On-chip in-application programmable FLASH memory

– Internal program/erase voltage generation

– Monitor ROM containing user callable program/erase routines

– FLASH security(2)

• On-chip random-access memory (RAM)

• 2-channel, 16-bit timer interface (TIM) module

• 6-channel, 10-bit analog-to-digital converter (ADC) with internal bandgap reference channel (ADC10)

• Up to 13 bidirectional input/output (I/O) lines and one input only:

– Six shared with KBI

– Six shared with ADC

– Two shared with TIM

– One input only shared with IRQ

– High current sink/source capability on all port pins

– Selectable pullups on all ports, selectable on an individual bit basis

– Three-state ability on all port pins

• 6-bit keyboard interrupt with wakeup feature (KBI)

– Programmable for rising/falling or high/low level detect

• Low-voltage inhibit (LVI) module features:

– Software selectable trip point

• System protection features:

– Computer operating properly (COP) watchdog

– Low-voltage detection with reset

– Illegal opcode detection with reset

– Illegal address detection with reset

• External asynchronous interrupt pin with internal pullup (IRQ) shared with general-purpose input pin

• Master asynchronous reset pin with internal pullup (RST) shared with general-purpose input/output (I/O) pin

• Memory mapped I/O registers

• Power saving stop and wait modes

• MC68HC908QY4A, MC68HC908QY2A and MC68HC908QY1A are available in these packages:

– 16-pin plastic dual in-line package (PDIP)

– 16-pin small outline integrated circuit (SOIC) package

– 16-pin thin shrink small outline packages (TSSOP)

• MC68HC908QT4A, MC68HC908QT2A and MC68HC908QT1A are available in these packages:

– 8-pin PDIP

– 8-pin SOIC

– 8-pin dual flat no lead (DFN) package