56F8014 General Description

• Up to 32 MIPS at 32MHz core frequency

• DSP and MCU functionality in a unified, C-efficient architecture

• 16KB Program Flash

• 4KB Unified Data/Program RAM

• One 5-channel PWM module

• Two 4-channel 12-bit ADCs

• One Serial Communication Interface (SCI) with LIN slave functionality

• One Serial Peripheral Interface (SPI)

• One 16-bit Quad Timer

• One Inter-Integrated Circuit (I2C) Port

• Computer Operating Properly (COP)/Watchdog

• On-Chip Relaxation Oscillator

• Integrated Power-On Reset and Low-Voltage Interrupt Module

• JTAG/Enhanced On-Chip Emulation (OnCE™) for unobtrusive, real-time debugging

• Up to 26 GPIO lines

• 32-pin LQFP Package

56F8014 Features

Digital Signal Controller Core

• Efficient 16-bit 56800E family Digital Signal Controller (DSC) engine with dual Harvard architecture

• As many as 32 Million Instructions Per Second (MIPS) at 32MHz core frequency

• Single-cycle 16 × 16-bit parallel Multiplier-Accumulator (MAC)

• Four 36-bit accumulators, including extension bits

• 32-bit arithmetic and logic multi-bit shifter

• Parallel instruction set with unique DSP addressing modes

• Hardware DO and REP loops

• Three internal address buses

• Four internal data buses

• Instruction set supports both DSP and controller functions

• Controller-style addressing modes and instructions for compact code

• Efficient C compiler and local variable support

• Software subroutine and interrupt stack with depth limited only by memory

• JTAG/Enhanced On-Chip Emulation (OnCE) for unobtrusive, processor speed-independent, real-time debugging