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F3861DM中文资料
F3861DM数据手册规格书PDF详情
Description
The Fairchild F3861 Peripheral Input/Output (PIO) device
provides two 8-bit HO ports, external interrupt, and a pro-
grammable timer. An 8-bit wide bidirectional data bus
transfers HO data bytes between the F3870 Central
Processing Unit (CPU) and the PIO.
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F3861DM 芯片相关型号
- 6300FC-8771000
- 6300FC-877U1000
- 833471522
- 833471622
- F3861A
- F3861B
- F3861C
- F3861D
- F3861E
- F3861PC
- HL2G221MCYS4WPEC
- HL2G221MCZS2WPEC
- HL2G221MLV50EC
- HL2G270MLS20EC
- HL2G271MCXS5WPEC
- HL2G271MCXS6WPEC
- HL2G271MCYS4WPEC
- HL2G271MCYS5WPEC
- HL2G271MCZS2WPEC
- TPE03GHC
- UPA2590
- UPA2590T1H-T1-AT
- UPA2590T1H-T2-AT
- UPA2591T1H
- UPA2591T1H-T1-AT
- UPA2591T1H-T2-AT
- UPA2592T1H
- UPA2592T1H-T1-AT
- UPA2593T1H-T1-AT
- UPA2593T1H-T2-AT
FAIRCHILD相关芯片制造商
Datasheet数据表PDF页码索引
- P1
- P2
- P3
- P4
- P5
- P6
- P7
- P8
- P9
- P10
- P11
- P12
- P13
- P14
- P15
- P16
- P17
- P18
- P19
- P20
- P21
- P22
- P23
- P24
- P25
- P26
- P27
- P28
- P29
- P30
- P31
- P32
- P33
- P34
- P35
- P36
- P37
- P38
- P39
- P40
- P41
- P42
- P43
- P44
- P45
- P46
- P47
- P48
- P49
- P50
- P51
- P52
- P53
- P54
- P55
- P56
- P57
- P58
- P59
- P60
- P61
- P62
- P63
- P64
- P65
- P66
- P67
- P68
- P69
- P70
- P71
- P72
- P73
- P74
- P75
- P76
- P77
- P78
- P79
- P80
- P81
- P82
- P83
- P84
- P85
- P86
- P87
- P88
- P89
- P90
- P91
- P92
- P93
- P94
- P95
- P96
- P97
- P98
- P99
- P100
- P101
- P102
- P103
- P104
- P105
- P106
- P107
- P108
- P109
- P110
