General Description

The 100331 contains three D-type, edge-triggered master/slave flip-flops with true and complement outputs, a Common Clock (CPC), and Master Set (MS) and Master Reset (MR) inputs. Each flip-flop has individual Clock (CPn), Direct Set (SDn) and Direct Clear (CDn) inputs. Data enters a master when both CP n and CPC are LOW and transfers to a slave when CP n or CPC (or both) go HIGH. The Master Set, Master Reset and individual CDn and SDn inputs override the Clock inputs. All inputs have 50 kΩ pull-down resistors.

Features

■ 35 power reduction of the 100131

■ 2000V ESD protection

■ Pin/function compatible with 100131

■ Voltage compensated operating range = −4.2V to −5.7V

■ Available to industrial grade temperature range